"Achieving Ultra High Quality and Reliability in Deep Sub-Micron Technologies using Metal Layer Configurable Platform ASICs"

R. Madge , M. Vilgis, and V. Bhide
LSI Logic Corporation

Abstract

In Deep Sub-Micron CMOS technologies it has become increasingly difficult to achieve the aggressive quality and reliability goals required by the end customer. This is due to the increasingly complex process technologies, the growing number of design features and the reduced effectiveness of test and reliability screens such as burn-in. LSI Logic's metal layer configurable Platform ASIC achieves ultra high reliability even in complex products using a two pronged strategy towards defect avoidance and tolerance:

1. Design for Reliability and tolerance to intrinsic and extrinsic failure mechanisms:

Designing for tolerance to Deep Sub-Micron effects such as Via stress Migration, Soft Error Rate, Negative Bias Temperature Instability (NBTI) is critical to meeting the long term Intrinsic Reliability goals as well as the infant mortality requirements. Platform ASIC allows the structure of the Logic and Memory design to be built with maximum robustness to these Deep Sub-Micron failure mechanisms by following conservative design rules in locations of higher risk of failure or degradation. Also pre-routing and pre-verification of LSI Logic’s Coreware® IP ensures that performance and reliability is characterized across the whole process and design window using test chips specifically designed to understand fail rates at statistically valid confidence levels. Soft Error Rate vulnerability in the configurable logic of a Platform ASIC is much lower than on Field Programmable Logic Devices due to the fact that the logic is 100% non-volatile and does not require SRAM to store the program code.

2. High Test Defect Coverage and maximum screening efficiency for all defect categories:

High fault coverage for stuck-at faults is not sufficient. Also burn-in screening does not adequately target resistive defects and is prone to thermal runaway and EOS. High defect coverage of bridging defects, transition delay faults and leakage mechanisms using multiple detect test vectors running at maximum clock frequency and the ability to screen all of the outlier or “maverick” die is critical to meeting the quality and reliability goals. In addition targeting of latent defects using statistical prediction and neighborhood methods is key. LSI Logic Platform ASIC test methodology achieves high fault coverage in all defect categories and LSI Logic's Statistical Post-Processing of the test data removes all the outliers and also die in areas of high statistical probability of latent defects and reliability failures.

 

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