"The Impact of Silicon Etch Dislocations on
EEPROM Cell Data Retention Reliability"
The relationship between silicon etch dislocations and EEPROM cell data retention reliability will be discussed in this paper. The point of view is from ZMD’s own floating gate EEPROM design, process yield, field experience and failure analysis efforts. Silicon dislocations occur naturally in many CMOS semiconductor processes but have a greater impact on IC reliability at high operating temperatures common in high reliability applications. The use of wafer level high temperature screens will be discussed focusing on their use to reduce PPM defect levels. A detailed review of an EEPROM cell failure will be discussed and how this evaluation utilized the 8D approach to aid problem solving and the development of subsequent corrective actions.
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