Dynamic High-Performance Multi-Mode Architectures for AES Encryption

Eric Swankoski
Space Systems Development
Naval Research Laboratory

Vijaykrishnan Narayanan
Computer Science & Engineering
The Pennsylvania State University


With bandwidth and throughput capabilities of modern optical networks increasing rapidly, it is becoming more and more important to not only protect the data utilizing these networks but also provide optimal throughput. Encryption of transmitted packets using the AES encryption algorithm provides both superior strength and efficiency when compared to other symmetric encryption methods as well as standard public key algorithms. Typical optical links have throughput capacities that range from tens of gigabits per second to hundreds of gigabits per second. Even with modern FPGAs rapidly evolving in terms of both silicon area efficiency and performance, conventional architectures do not offer the throughput required for efficient use of optical links.

We study several alternative implementations of the AES algorithm on Xilinx Virtex-II and Virtex-4 FPGAs. The algorithm is flexible enough to allow multiple implementations and multiple encryption modes as well as support different degrees of pipelining. Typical encryption pipelines perform several operations a single round of encryption - per pipeline stage; more advanced and higher-performance encryption pipelines utilize pipelining within each round of encryption. Additionally, the nonlinear transformation utilized by the AES algorithm has multiple possible implementations. We study the performance and efficiency of deeply pipelined encryption architectures with varying degrees of reconfigurability. We show that throughputs of more than 61 Gb/s can be achieved using various encryption modes, including electronic codebook mode, counter mode, and staggered cipher-block chaining mode.

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