"Leveraging Software to Enhance Timing Analysis for Actel RTAX-S Devices"
This poster presentation will explore the new features of the improved Actel gate-level static timing analysis tool, SmartTime. SmartTime enables complete timing analysis and timing constraints editing for RTAX-S designs to achieve timing closure easier. It provides a selection of analysis types including finding the minimum cycle time that does not result in a timing violation; identifying paths with timing violations; analyzing delays of paths that have no timing constraints; performing inter-clock domain timing verification; performing maximum and minimum delay analysis for setup and hold checks; checking the timing requirements for violations while taking into account timing exceptions such as multicycle or false paths. Overall, SmartTime provides both new and improved features to aid designers achieve timing closure for their designs.
2005 MAPLD International Conference Home Page