"Toward Single-Electron Nanonetworks and Architectures"
C. Gerousis and D. Ball
Christopher Newport University
It is a known fact that shrinking transistor size has given rise to the vast advancement in microelectronics. It is generally accepted also that device scaling will ultimately reach a limit imposed by the laws of physics. The main challenge then is to develop nanodevices that will extend scaling beyond roadmap projections. Such devices, based on the controllable transfer of charge between dots or ‘islands’, can take advantage of the quantum mechanical effects, such as tunneling and energy quantization, which would normally occur at the nanometer scale. Several emerging nanoscale device replacements for bulk-effect semiconductor transistor have been suggested to overcome the problems accompanied by scaling. Among the new devices is the single electron tunneling (SET) transistor that offers attractive features such as reduced dimensions, high integration density, and low power consumption. This paper investigates the use of SETs for potential application in future high density and low power neural networks. We first present a neural network based on single-electron threshold logic. We then use Monte Carlo (MC) simulation results to show the behavior of the network in an attempt to realize an image processing application.
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