Ronald Reagan Building and International Trade Center
September 8-10, 2004
Session J. will be in an informal workshop format, open to all MAPLD attendees. The structure for this session will be a combination of talks and discussions in a small group setting.
Wednesday, September 8, Starting at 2: 15 pm
Jay C. Schaefer, Department of Defense
Kay Jobe, Boeing
2:15 pm Submission 149
"Effective Post-Programming Screening of Antifuse FPGAs for Space Applications"
Yasuo Sakaide, Kimiharu Kariu, Kenji Numata, Akihisa Tsukino, Mikihiko Urano, Kenichi Chiba, Kenji sugimoto, Yoshihisa Tsuchiya, and Toshifumi Arimitsu
High Reliability Components Corporation
Short Abstract: sakaide_short_a.doc
2:30 pm Submission 126
"Low Temperature Life Test Effects on the Aeroflex ViaLink FPGA"
Aeroflex Colorado Springs
2:45 pm Submission 1002
"Propagation Delay Stability in Logic Devices"
NASA Office of Logic Design
2:45 pm Panel Discussion for Papers 149, 126, and 1002 3:30 pm Break In The Atrium Hall; Dedicated Industrial and Government Exhibits 4:45 pm 5:10 pm 5:35 pm
"The Negative Impact of Lead-Free Products on Aerospace and Military Electronics Reliability"
Andrew D. Kostic1 and Charlie 2
6:00 pm End of Day 1
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