Ronald Reagan Building and International Trade Center
Washington, D.C.
September 8-10, 2004
Session J. will be in an informal workshop format, open to all MAPLD attendees. The structure for this session will be a combination of talks and discussions in a small group setting.
Wednesday, September 8, Starting at 2: 15 pm
Hemisphere A
Session Chairs:
Jay C. Schaefer, Department of Defense
Kay Jobe, Boeing
2:15 pm Submission 149
"Effective Post-Programming Screening of Antifuse FPGAs for Space Applications"
Yasuo Sakaide, Kimiharu Kariu, Kenji Numata, Akihisa Tsukino, Mikihiko Urano, Kenichi Chiba, Kenji sugimoto, Yoshihisa Tsuchiya, and Toshifumi Arimitsu
High Reliability Components Corporation
Short Abstract: sakaide_short_a.doc
Presentation: j149_sakaide_s.ppt
Paper: p149_sakaide_p.doc2:30 pm Submission 126
"Low Temperature Life Test Effects on the Aeroflex ViaLink™ FPGA"
Ron Lake
Aeroflex Colorado Springs
Abstract: lake_1_a.doc
Presentation: j126_lake_s.ppt2:45 pm Submission 1002
"Propagation Delay Stability in Logic Devices"
Rich Katz
NASA Office of Logic Design
Abstract: katz3_a.html
Presentation: j1002_katz_s.ppt2:45 pm Panel Discussion for Papers 149, 126, and 1002 3:30 pm Break In The Atrium Hall; Dedicated Industrial and Government Exhibits 4:45 pm Submission 182
"An Unobtrusive Debugging Methodology for Actel AX and RTAX-S FPGAs"
Jonathan Alexander
Actel Corp.
Abstract: alexander_a.pdf
Presentation: j182_alexander_s.ppt5:10 pm Submission 120
"Maintaining Data Integrity in EEPROM’s"
Ed Patnaude
Maxwell Technologies
Abstract: patnaude_a.pdf
Presentation: j120_patnaude_s.ppt5:35 pm Submission 103
"The Negative Impact of Lead-Free Products on Aerospace and Military Electronics Reliability"
Andrew D. Kostic1 and Charlie 2
1 Northrop-Grumman
2 BMPCOE/Willcor
Abstract: kostic_a.doc
Presentation: j103_kostic_s.ppt6:00 pm End of Day 1
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February 03, 2010
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