Richard B. Katz
NASA Office of Logic Design
This paper will present data on propagation delays in logic devices, examining their distributions, the effects of life on propagation delay, and the characteristics of the changes in delays. Factory life test/qualification data will be presented along with recently taken in the evaluation of damage to programmed antifuses.
Analysis of the data will be used to examine existing design rules, but for min/max analysis as well as those pertaining to the relative changes in delays.
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