NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Please e-mail comments and suggestions for these guidelines and criteria.

Design Guidelines and Criteria


Space Flight Digital Electronics

Special Pins

One of the most common problems identified during design reviews is the improper termination of special pins.  For every device, the data sheet and design schematics should be carefully reviewed such that it can be shown that each special pin is properly terminated.  Termination of many of these special pins can not be verified by test.

A. MODE Pin.  This pin, present on early generation of Actel devices, must be grounded.  It is recommended that this pin be grounded with a 10 kohm resistor and a hard jumper to ground in parallel, with the default setting the hard ground installed.

B. JTAG Interface: Many modern digital microcircuits have this interface.  One optional pin, which is highly desired for high-reliability designs, is the TRST*.  If present, this must be hard grounded since the IEEE 1149.1 specification requires a pull-up resistor inside of the part.  Use of a pull-down resistor, such as what some people use for the MODE pin, can result in the TRST* pin's input voltage being at or above the logic threshold.  If the TRST* pin is not present, then the TCLK should be a free-running independent system clock with TMS held to a logic '1'.  Do not use the system clock as the TCLK input, because during a malfunction, the chip's operational clock input may turn into an output and clamp the clock.

C. Unused Inputs: In general, all devices should have properly terminated inputs.  For normal CMOS devices, this is a requirement.  Certain programmable devices such as FPGAs will often take care of unused pins via software, exploiting the programmable nature of the microcircuit.  However, the "fine print" for each pin must be read carefully.  For example, in Actel SX and SX-S, clock inputs such as HCLK or the global routed clocks do not have an output stage -- they are special purpose -- and thus must be terminated by the user.  Failure to do so can result in large currents.  As another example, unused LVDS receiver inputs should be left unconnected, as advised by the UTMC documentation.  Depending on the device, pins labeled as "N/C" may be used for internal purposes and terminating them on the board may result in problems; conversely, not terminating "N/C"'s in certain cases can be bad.  Check each pin carefully according to the specification and contact the manufacturer if necessary.

D. Test Interface: Many devices have custom test interfaces and will have to be handled on a case-by-case basis.  Since they hook up to test equipment, care should be taken in following the manufacturer's instructions.  For example, Actel SX-S device test pins should be series terminated.  Other device pins, such as inputs, should be terminated; others have internal terminations.  There are no general rules.

E. Configuration Pins: Ensure that each configuration pin is carefully checked against the latest data sheet.  Some pins have very high internal pullup resistors and can be switched by high-speed signals on the board level; design defensively and ensure that the levels are solid.  Also, some configuration pins can naturally just happen to float to the desired state with nominal operation observed.  Lastly, beware of special pins such as programming pins that are required to be terminated appropriately for flight.

F. Others: Different devices will have different pins and there is no overriding, general rule, other than that each pin must be checked.

References, Notes, and Related Documents

  1. It is critical to ensure that all pins are properly terminated.  Some will affect the functionality of the chip and these may or may not be caught in test.  Some unterminated pins will have parametric and perhaps long-term reliability effects.  As an example of this, please view the following plot showing unconnected clock pins in the total dose environment.  clock_unterminated.gif

  2. "Special Pins" from "Advanced Design: Designing for Reliability," presented at the 2001 MAPLD International Conference, Laurel, MD, September 2001.
  3. "TRST* and the IEEE JTAG 1149.1 Interface,", OLD News #7, January 2003.
  4. "Terminators for Silicon Explorer," OLD News #1.
  5. "Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry."  This white paper reviews basic 1149.1 principles, radiation results on SX Series devices, and finishes with mitigation techniques and design considerations.
  6. "GROUND THE MODE PIN NOW!!!!!!!!!!!!!!!!!!!!!," Termination of MODE Pins in Actel Field Programmable Gate Arrays.

  7. Issue on the use of the SDI and DCLK pins in some date codes of the RH1020 and RT1020s.  Please see the  RH1020 Special Pins Advisory and the SDI Report.

TOP LEVEL: "Design Guidelines and Criteria for Space Flight Digital Electronics"

Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz