Please e-mail comments and suggestions for these guidelines and criteria.
VI. Hazard Analysis
A static hazard exits when a change to a single variable to a combinational network causes a transient or momentary change in other variables to occur, which should not occur (e.g., 1 ® 0 ® 1) then a static hazard is present. Normally this is not a problem in synchronous design as long as there is sufficient time for the signals to settle. A similar condition, a dynamic hazard, exists if there is a transition of the form 1 ® 0 ® 1 ® 0. That is, it did not switch cleanly. Any circuit free of static hazards will be free of dynamic hazards. Essential hazards are out of scope of this discussion.
This topic is not covered in many logic classes and with the use of HDLs and functional simulation many designers are not familiar with these concepts. For 100% synchronous designs with a single clock and a common edge there are normally no concerns. Yet during reviews hazards are often present, unknown to the designer. One example of this is the use of TMR circuits to generate a clock signal to a finite state machine. The change in one input to the voter, there to mitigate the effects of SEUs, can result in a double clock from the "glitch" coming out of the voter, unless the voter is hazard free. Often a component will appear to be hazard free; one must look carefully at the implementation in the logic family that you are using. For example, are multiplexors, the foundation of some FPGA families glitch free? There is no guarantee that they will be and hence can not be considered safe clock generators without a lot of care. Another example is when a voted output is brought off-chip and used as a clock input for an external device. Logic synthesizers have been observed to generate hazards in the circuits they generate, unknown to the engineer running the tool.
References, Notes, and Related Documents
"Hazards," from Advanced Design: Designing for Reliability, 2001 MAPLD International Conference, Laurel, MD, September 10, 2001.
- Analysis and Design of Digital Circuits and Computer Systems, Paul M. Chirlian, Stevens Institute of Technology, ©1976. pp. 261-264.
TOP LEVEL: "Design Guidelines and Criteria for Space Flight Digital Electronics"
NASA Office of Logic Design
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