Acknowledgements: A special thanks to Ben "VHDLCohen" for a number of these links.
Arithmetic Module Generator for High Performance VLSI Designs 

VHDL Library of Arithmetic Units 

Distributed Arithmetic  Abstract Distributed arithmetic is a bit level rearrangement of a multiply accumulate to hide the multiplications. It is a powerful technique for reducing the size of a parallel hardware multiplyaccumulate that is well suited to FPGA designs. It can also be extended to other sum functions such as complex multiplies, fourier transforms and so on. 
Multiplication in FPGAs  Abstract Multiplication is basically a shift add operation. There are, however, many variations on how to do it. Some are more suitable for FPGA use than others. This page is a brief tutorial on multiplication hardware. 
Distributed Arithmetic  Abstract Distributed arithmetic is a bit level rearrangement of a multiply accumulate to hide the multiplications. It is a powerful technique for reducing the size of a parallel hardware multiplyaccumulate that is well suited to FPGA designs. It can also be extended to other sum functions such as complex multiplies, fourier transforms and so on. 
Multiplication in FPGAs  Abstract Multiplication is basically a shift add operation. There are, however, many variations on how to do it. Some are more suitable for FPGA use than others. This page is a brief tutorial on multiplication hardware. 
LEON Division 
A European Space Agency have developed a processor named Leon. Synthesizable VHDL model of the processor is also made available. The project involves design and implementation of one of the following arithmetic units in two technologies; FPGA and Synopsys standard library. 
fp_divider.pdf 

http://www.eng.uci.edu/~alberto/PhDdiss/an99phd.pdf  Low Power Division and Square Root Abstract 
dh_arith_97.pdf  SRT Division Architectures and Implementations SRT dividers are common in modern floating point units. Higher division performance is achieved by retiring more quotient bits in each cycle. Previous research has shown that realistic stages are limited to radix2 and radix4. Higher radix dividers are therefore formed by a combination of lowradix stages. In this paper, we present an analysis of the effects of radix2 and radix4 SRT divider architectures and circuit families on divider area and performance. We show the performance and area results for a wide variety of divider architectures and implementations. We conclude that divider performance is only weakly sensitive to reasonable choices of architecture but significantly improved by aggressive circuit techniques. Lang [5] analyze the tradeoffs of using several of these optimizations in the context of static CMOS standardcells. Williams [8] presents a selftimed dynamic CMOS divider comprising a ring of five radix2 stages that incorporates several of these techniques, and he also presents an analysis of the performance and area effects of the architectural components. Prabhu [9] presents the tradeoffs encountered when designing the Sun UltraSparc radix8 divider. In contrast to previous works, this paper analyzes in detail the effects of both circuit style and divider architecture on the area and performance of divider implementations. We present the performance results using the technologyindependent 
The CORDIC Algorithm  Summary CORDIC is an acronym for COrdinate Rotation DIgital Computer. It is a
class of shiftadd algorithms for rotating vectors in a plane. In a nutshell, the CORDIC
rotator performs a rotation using a series of specific incremental rotation angles
selected so that each is performed by a shift and add operation. 
Tanya Vladimirova 
Abstract This paper is concerned with FPGA implementation of CORDIC schemes for fast and silicon area efficient computation of the sine and cosine functions. The results of theoretical investigation into redundant CORDIC are presented. Summary of CORDIC synthesis results based on Actel and XILINX FPGAs is given. Finally applications of CORDIC sine and cosine generators in small satellites are discussed. Keywords 
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