Jump to: EEE Links Archive.
Note: Many of the links here are to the rk.gsfc.nasa.gov site and haven't been moved yet. If you have any problems accessing any information, please contact me at richard.b.katz@nasa.gov.
J.J. Wang, W. Wong, S. Wolday, B. Cronquist, J. McCollum, R. Katz, and I. Kleyner |
Abstract The single event effects and hardening of a 0.15 µm antifuse FPGA, the AX device, were investigated by beam test and computer simulation. The beam test showed no permanent damage mode. Functional failures were observed and attributed to the upsets in a control logic circuit, the startup sequencer. Clock upsets were observed and attributed to the single event transients in the clock network. Upsets were also measured in the user flip-flop and embedded SRAM. The hardening technique dealing with each upset mode is discussed in detail. SPICE and three-dimensional mixed-mode simulations were used to determine the design rules for mitigating the multiple upsets due to glancing angle and charge sharing. The hardening techniques have been implemented in the newly fabricated RTAXS device. Preliminary heavy-ion-beam test data show that all the hard-wired hardening solutions are working successfully. |
Papers from the 2003 IEEE Nuclear and Space Radiation Effects Conference |
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| MAPLD
Con 2002 MAPLD Con 2001 MAPLD Con 2000 MAPLD Con 1999 MAPLD Con 1998 |
Papers from the MAPLD International Conferences |
Jih-Jong Wang1, Brian Cronquist1, John McCollum1, Wanida Parker1, Rich Katz2, and Igor Kleyner1 1Actel Corporation HEART/GOMAC 2002 |
Abstract The total dose performance of the antifuse FPGA for space applications is summarized. Optimization of the radiation tolerance in the fabless model is the main theme. Mechanisms to explain the variation in different products are discussed. |
Bryan S. Goda1, Russel P. Kraft2, Steven R. Carlough3, Thomas W. Krawczyk Jr.4, and John F. McDonald2 1United States Military Academy 1999 First NASA/DOD Workshop on Evolvable Hardware, pp. 59-69 |
Abstract Field programmable gate arrays (FPGAs) are flexible programmable devices that are used in a wide variety of applications such as network routing, signal processing, pattern recognition and rapid prototyping. Unfortunately, the flexibility of the FPGA hinders its performance due to the additional logic resources required for the programmable hardware. Today's fastest FPGAs run in the 250 MHz range. This paper proposes a new family of FPGAs utilizing a high-speed SiGe Heterojunction Bipolar Transistor (HBT) design, co-integrated with CMOS in an IBM BiCMOS process. This device is bit-wise compatible with the Xilinx 6200, with operating frequencies in the 1 to 20 GHz range. All logic and routing in this new design is multiplexer based, eliminating the need for pass transistors, the main roadblock to high speed in today's FPGAs. |
Goda, B.S.; McDonald, J.F.; Carlough, S.R.; Krawczyk, T.W., Jr.; Kraft, R.P. IEE Proceedings - Computers and Digital Techniques, May 2000 |
Abstract: Field programmable gate arrays (FPGAs) are flexible programmable devices that are used in a wide variety of applications. The flexibility of the FPGA hinders its performance due to the additional logic resources required for programmable hardware. The paper proposes a high speed SiGe heterojunction bipolar transistor (HBT) FPGA design co-integrated with CMOS in an IBM BiCMOS process. This device would be bitwise compatible with the Xilinx 6200, with operating frequencies in the 1-20 GHz range. To reduce power dissipation, the configuration bits used to define the FPGA's function will be stored in CMOS memory. Further power savings can be accomplished by integrating CMOS control into bipolar current trees and using a switchable current mirror to turn off unused current trees. The speed of bipolar combined with power savings of CMOS can now be merged to produce a new family of high speed FPGAs. |
Joseph A. Hoffman, Scott Doyle and Jon Maimon Government Microcircuit Applications Conference Digest |
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| Force_Errors.pdf | Forcing Signal Errors with VHDL Abstract This paper presents a technique, which uses the user-defined resolution function feature of VHDL, to selectively control from VHDL the assertion of errors imposed on testbench signals of type Std_Logic. This technique allows the testbench environment to selectively inject errors at specific times and with specific values onto signals to verify the design-under-test responses to interface errors. (January 4, 2001) |
| Everett_WIRE.doc Everett_WIRE.PDF |
Recovery of the Wide-Field Infrared Explorer Spacecraft Abstract |
| EDAC8Cyclic.pdf edac.vhd edac_rtl.vhd edac_tb.vhd |
A (16,8) Error Correcting Code (T=2) For Critical Memory
Applications Abstract High density SRAMs generate errors in their stored data because of natural radiation. This is a particular problem for computing on-board a satellite , where the single-error correction of the usual Hamming code can be inadequate. The two-bit error correcting code described here is a more powerful and efficient alternative. (12/21/2000) |
| Component_Verification.pdf | Component Verification by Example Abstract This paper presents, by example, some of the key features of the front-end processes for specifying the planning of both the implementation and verification (i.e., testbench) of a design to ensure that the implemented design meets its intended requirements and costs. (12/19/2000) |
| Xilinx_NSREC2000.pdf | Radiation Characterization, and SEU Mitigation, of the Virtex
FPGA for Space-Based Reconfigurable Computing Abstract Orbital remote sensing instruments and systems benefit from high performance, adaptable computing systems. Field programmable SRAM-based gate arrays (FPGAs) are usually the chosen platform for real-time reconfigurable computing. This technology is driven by the commercial sector, so devices intended for the space environment must be adapted from commercial product. Total ionizing dose, heavy ion and proton characterization have been performed on Virtex FPGAs fabricated on epitaxial silicon to evaluate the on-orbit radiation performance expected for this technology. The dominant risk is Single Event Upset (SEU), so upset detection and mitigation schemes have also been tested to validate the improvement in the device upset sensitivity and the system consequence of upsets. (10/28/2000) |
| desplats2.pdf | Internal Testing of Programmable Circuits Abstract The growing use of programmable circuits has made it necessary to perform accurate debug and internal testing of these circuits. To meet this challenge, we have developed an innovative method to investigate the internal functionality of programmable circuits. (9/15/2000) |
| Technical_Program - MAPLD 1999 | Papers from the MAPLD 1999 International Conference. |
| A4_Katz_P.pdf A4_Katz_P_Scanned.doc 1999
MAPLD International Confernce |
Logic Design Pathology and Space Flight Electronics Abstract Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems. (added February 9, 2000). |
| D2_Kleyner_P.pdf | System-On-Chip Data Processing and Data Handling Spaceflight Electronics Abstract This paper presents a methodology and a tool set which implements automated generation of moderate-size blocks of customized intellectual property (IP), thus effectively reusing prior work and minimizing the labor intensive, error-prone parts of the design process. Customization of components allows for optimization for smaller area and lower power consumption, which is an important factor given the limitations of resources available in radiation-hardened devices. The effects of variations in HDL coding style on the efficiency of synthesized code for various commercial synthesis tools are also discussed. (added February 9, 2000). |
| NSREC99_SRAM.pdf NSREC99_SRAM.doc (scanned in, .doc is larger but better quality than the .pdf) |
SRAM Based Re-programmable FPGA for Space Applications Abstract An SRAM-based re-programmable FPGA is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 um CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of a SEU on the device operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET. Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC at the device level are presented. For the configuration SRAM cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL. With regard to ionizing radiation effects, the increase in static leakage current measured indicates a device tolerance of approximately 50 krad(Si). |
NSREC99_Effects.PDF NSREC99_Effects.doc (scanned in, .doc is larger but better quality quality than the .pdf) |
The Effects of Architecture and Process on the Hardness of
Programmable TechnologiesApplication of Field Programmable Gate Arrays to Space Projects Abstract Architecture and process, combined, significantly affect the hardness of programmable technologies. The effects of high energy ions, ferroelectric memory architectures, shallow trench isolation are investigated. A detailed latchup study has been performed. |
| NSREC99_Software.PDF NSREC99_Software.doc (scanned in, .doc is larger but better quality than the .pdf) |
The Impact of Software and CAE Tools on SEU in Field Programmable Gate Arrays Programmable Gate Arrays to Space Projects Abstract Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements. |
| chiba1.pdf chiba1.doc |
Application of Field Programmable Gate Arrays to Space Projects Abstract Field Programmable Gate Arrays (FPGAs) which are designed for ground usage will be applied in several space projects. HIREC performed anionizing radiation test for Actel's anti-fuse type non-radiation hardened FPGA, A1280A, to demonstrate an applicability of the FPGA for space projects. We performed the test with low dose rate to the prevent an excessive trapped hole effect. |
| bezerra1.pdf | Improving the Dependability of Embedded Systems Using Configurable Computing Technology Abstract In this work, strategies for dependability improvement of embedded systems based in configurable computing technology are discussed. To better explore the possibilities, an embedded system for space application was chosen as a case study. The case study was first implemented in a high level of abstraction, using the VHDL language, targeting its utilisation in a situation where no fault tolerant requirements were needed. The requisites to increase the reliability and testability of this system are discussed here, as well as some expected results. |
| gingrich1.pdf | Total Ionizing Dose Effects in a SRAM-Based FPGA Abstract We have measured the effects of total ionizing dose on Xilinx XC4036X FPGAs. The FPGAs were irradiated at a dose rate of about 0.5 krad/hr. An average total dose of 39 krad(Si) and 16 krad(Si) were absorved by the XL-series and XLA-series FPGAs, respectively, before the power supply current increased. |
| gingrich2.pdf | Irradiation of a FPGA in a Submircon CMOS Process Abstract We have measured the effects of total ionizing dose on a XC4036XL-1HQ240C. The FPGA operated without error for 115 days while being irradiated with a dose rate of 87 rad(Si)/hr. A total dose of (236 +/-11) krad(Si) was absorbed before the first error occurred. |
| 256k_eeprom.pdf |
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| Papers by Ray Andraka | Link to publications by Ray Andraka. |
| NASA_Data_Processing.pdf | Extending NASA’s Data Processing to Spacecraft Abstract Over the past few decades, advances in ground-based processing and space-to-Earth links have fallen further behind NASA’s requirements for handling obser-vation data. Thus NASA’s ability to observe and capture Earth phenomena of theoretical and practical interest far outstrips its ability to transfer, process, or store such data. Increasing the on-board computing power of spacecraft is one solution that may allow both space and ground-based systems to address these limitations. |
| SpaceWire.pdf | SpaceWire: The Standard Abstract SpaceWire is an emerging standard for high-speed data handling which is intended to meet the needs of future, high-capability, remote sensing instruments. SpaceWire is based on two existing commercial standards, IEEE-1355 and LVDS which have been combined and adapted for use on-board spacecraft. This paper provides a detailed description of the proposed SpaceWire standard. The paper begins with an overview of the requirements for high-speed data links on-board a spacecraft. The SpaceWire standard is then described in some detail. Issues that need to be resolved before the draft standard can be issued to the space industry for comment are highlighted. Finally the current and future work on the standard are summarised. It should be noted that the information given in this paper is preliminary and likely to change. The intention here is to give visibility of the current state of the standard to European Space Industry and to encourage comment and criticism of the proposed standard. SpaceWire is the result of the efforts of many individuals within the European Space Agency, European Space Industry and Academia. The ESA Digital Interface Circuit Evaluation (DICE) study, led by the University of Dundee, has tested LVDS with IEEE-1355 and is now drafting the SpaceWire standard document. |
| A Self-Reconfiguring Computer System | PhD thesis: A Self-Reconfiguring Computer System Abstract In the fast-paced field of computing new technologies appear, are developed and then become outdated all within a few years. The underlying architectural precepts on the other hand remain relatively constant. Modern CPUs use the same sequential execution model which has been with us since Von Neumann. The latest processors use performance features such as caching, deep pipelining and register scoreboarding which are really only minor adaptations of techniques which have been used for twenty years. Reconfigurable logic arrays give us the opportunity to embrace an entirely new approach to computing. The technology is still young so there is a great deal to be done before this new medium reaches the maturity of conventional processors. Current reconfigurable logic arrays are limited to specialised custom computing tasks and are not suitable for the wide variety of tasks which general purpose computers tackle. This thesis demonstrates that reconfigurable processors do have the potential to entirely replace conventional processors. The Switchblade system described is a complete standalone general-purpose computer based entirely around a reconfigurable logic array. It lacks only hardware implementation and appropriate software to make it a realisable system. A significant aspect of this thesis is that it points the way to a major paradigm shift in the way computations can be performed. Instead of devising algorithms to run on and exploit a given computer architecture, an architecture is defined dynamically to perform the computation. While much work is still required the conceptual framework presented here paves the way for exciting future developments. |
| LaBel_DRAM98.pdf | Anatomy of an In-flight Anomaly: Investigation of Proton-Induced SEE Test Results for Stacked IBM DRAMs Abstract [This paper primarily deals with stacked IBM DRAMS. One section is dedicated to FPGAs and protons] Two antifuse-based field programmable gate array (FPGA) devices were also investigated for low sensitivity to proton-induced events: the Actel A1280A and RH1020 devices. |
| DSP_Study.pdf | DSP (Demanding Space-based Processing!): The Path Behind and the Road Ahead Abstract There are a growing number of applications for digital signal and image processing in space. Often these applications are demanding in terms of the processing power required and in the complexity of the algorithms that must be implemented. DSP (Digital Signal Processing) devices offer a blend of high performance and flexibility which is ideal for many of these demanding applications. This paper provides a brief introduction to digital signal processors and to their application in space. It then reviews the research and development activities leading to the the TSC21020E radiation tolerant, 32-bit, floating-point, DSP processor. Related research on multi-processor architectures and highly integrated DSP processor systems using multi-chip module technology is also reviewed. Two processing systems designed around the TSC21020E DSP processor for on-board signal and image processing applications are described. The paper goes on to summarise the current situation with regard to the use of DSP processors in space and then gives thought to future research and development activities. Future activities include developments to support efficient and effective use of the TSC21020E and standardisation of high-speed data handling interfaces. Finally, views about the next generation of DSP processors for space applications are given. |
| actel_sram_architecture99.pdf | A New High Density and Very Low Cost Reprogrammable FPGA Architecture (.pdf 122 kbytes) Abstract A new reprogrammable FPGA architecture is described which is specifically designed to be of very low cost. It covers a range of 35K to a million usable gates. In addition, it delivers high performance and it is synthesis effi-cient. This architecture is loosely based on an earlier reprogrammable Actel architecture named ES. By changing the structure of the interconnect and by making other improvements, we achieved an average cost reduction by a factor of three per usable gate. The first member of the family based on this architecture is fabricated on a 2.5V standard 0.25m CMOS technology with a gate count of up to 130K which also includes 36K bits of two port RAM. The gate count of this part is verified in a fully automatic design flow starting from a high level description followed by synthesis, technology mapping, place and route, and timing extraction. |
| NSREC98_Paper.pdf | Current Radiation Issues for Programmable Elements and Devices (.pdf 178 kbytes) Abstract State of the art programmable devices are utilizing advanced processing technologies, non-standard circuit structures, and unique electrical elements in commercial-off-the-shelf (COTS)-based, high-performance devices. This paper will discuss that the above factors, coupled with the systems application environment, have a strong interplay that affect the radiation hardness of programmable devices and have resultant system impacts in (1) reliability of the unprogrammed, biased antifuse for heavy ions (rupture), (2) logic upset manifesting itself as clock upset, and (3) configuration upset. General radiation characteristics of advanced technologies are examined and manufacturers’ modifications to their COTS-based and their impact on future programmable devices will be analyzed. |
| NSREC94.pdf | SEU Hardening of FPGAs for Space Applications and Device Characterization (.pdf 861 kbytes) Abstract FPGAs are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are anlalyzed and test methodology is discussed. |
| MRC_SEU.pdf | Temporally Redundant Latch for Preventing Single Event Disruptions in Sequential Integrated Circuits Abstract |
| Xilinx_NSREC98.PDF | Neutron Single Event Upsets In SRAM-Based FPGAs (.pdf 35kbytes) Abstract SRAM-based FPGAs have been studied for their sensitivity to atmospheric high energy neutrons. FPGAs with the supply voltage 5V and 3.3V were irradiated by 0-11, 14 and 100 MeV neutrons and showed a very low SEU susceptibility. |
| Shih_1997.pdf | Characterization and Modeling of a Highly Reliable Metal-to-Metal Antifuse for High-Performance and High-Density Field Programmable Gate Arrays (.pdf 894 kbytes) Abstract Reliability of a new amorphous silicon/dielectric antifuse is characterized and modeled. Unprogrammed antifuse leakage and time-to-breakdown are functions not only of applied voltage but also of stressing polarity and temperature. Both breakdown and leakage criteria are used to investigate their effects on time-to-fail. A thermal model incorporates the effects of programming and stress currents, ambient temperature, and variation of antifuse resistance with temperature. Measured temperature dependence of antifuse resistance is for the first time used to derive key physical parameters in the model. |
| EfficientFaultTolerance.pdf | Efficiently Supporting Fault-Tolerance in FPGAs (.pdf 118 kbytes) Abstract While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical design into a set of tiles. In response to a component failure, we capitalize on the unique reconfiguration capabilities of FPGAs and replace the affected tile with a functionally equivalent tile that does not rely on the faulty component. Unlike fixed structure fault-tolerance techniques for ASICs and microprocessors, this approach allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead. |
| LowOverheadFaultTolerance.pdf | Low Overhead Fault-Tolerant FPGA Systems (.pdf 108 kbytes) Abstract Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight. We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of FPGAs. The physical design is partitioned into a set of tiles. In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile. Unlike ASIC and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead. |
| "Radiation
Effects on Current Field Programmable Technologies" |
IEEE NSREC/Transactions on Nuclear Science, Dec., 1997.
(.pdf 315 kbytes) Abstract Manufacturers of field programmable gate arrays (FPGAs) take different technological and architectural approaches that directly affect radiation performance. Similar technological and architectural features are used in related technologies such as programmable substrates and quick-turn application specific integrated circuits (ASICs). After analyzing current technologies and architectures and their radiation-effects implications, this paper includes extensive test data quantifying various devices’ total dose and single event susceptibilities, including performance degradation effects and temporary or permanent re-configuration faults. Test results will concentrate on recent technologies being used in space flight electronic systems and those being developed for use in the near term. This paper will provide the first extensive study of various configuration memories used in programmable devices. Radiation performance limits and their impacts will be discussed for each design. In addition, the interplay between device scaling, process, bias voltage, design, and architecture will be explored. Lastly, areas of ongoing research will be discussed. |
| "Rad-Hard/Hi-Rel FPGA" | Third ESA Electronic Components Conference, April 1997 (.pdf 73 kbytes) Abstract This paper describes the attributes and goals for a radiation-hard and high-reliability Field Programmable Gate Array (FPGA). The first Qualified Manufacturer List (QML) radiation-hardened antifuse FPGA, RH1280, is characterized. Its total dose and Single Event Effects (SEEs) are tested and the results are reported. Trade-offs and limitations in Single Event Upset (SEU) hardening are also discussed. |
| "Diagnosis of Multiple Faults Using IDDQ Techniques" |
IEEE ITC, IDDQ Workshop, 1995 (.pdf 18 kbytes) Abstract A procedure for diagnosing faults using IDDQ techniques can identify leakage paths to power and ground as well as bridging faults. This diagnostic has been successfully applied to gate arrays with radiation-induced multiple faults. The feasibility of automating the procedure has been demonstrated and the underlying concepts appear compatible with certain design-for-test techniques. |
| "Antifuse FPGA for Space Applications." | RADECS '97. Testing Results and Analysis of Recent Antifuse (ONO and Metal-to-Metal) FPGAs for Space Applications. (.pdf 77 kbytes). Abstract This paper presents total dose and SEE testing data of recent antifuse products. It includes ONO-antifuse FPGAs: A1020B, A1020S, RH1020, A1280XL, A1460A, A14100A, A32140DX and A32200DX. Also included are preliminary results of pre-production metal to metal (M/M) antifuse FPGAs, the I100 and the RHI100. Finally, SEU rate calculations of Actel FPGAs are discussed. |
| "An Experimental Survey of Heavy Ion Induced Dielectric Rupture in Actel Field Programmable Gate Arrays" | RADECS '95. Data from Heavy Ion Antifuse Rupture Experiments. (.pdf 64 kbytes). Abstract Irradiations and subsequent failure analyses were performed to investigate single event dielectric rupture (SEDR) in Actel FPGAs as a function of ion LET (linear energy transfer), angle, bias, temperature, feature size, and device type. The small cross sections imply acceptably low risk for most spacecraft uses. |
| "Total Dose Responses of Actel 1020B and 1280A Field Programmable Gate Arrays (FPGAs)" | RADECS '95. Total Dose Responses of Actel 1020B and 1280A (.pdf 166 kbytes). Abstract Gamma irradiation and annealing of a large number of Actel FPGAs with in-situ current measurements were performed. Lot-to-lot, part-to-part, and burn in variations were measured. Findings include a catastrophic failure mechanism and minimal dose rate effects. |
| "Ionizing Radiation Response of an Amporphous Silicon Based Antifuse" | IEEE NSREC/Transactions on Nuclear Science, Dec., 1997. (.pdf 57 kbytes) Abstract |
| "Amorphous Silicon Antifuse Programmable Array-Logic Devices for High Reliability Space Applications" | GOMAC, March, 1998. (.pdf 36 kbytes) Abstract The reliability and radiation performance of programmable array logic (PAL) devices using amorphous silicon (a -Si) antifuses is examined. Accelerated life-test data on programmed PALs show a failure rate of less than 0.1 failures in one billion device hours (0.1 FITs). It is also shown that the resistance characteristics of a -Si antifuses either improves with increasing radiation dose (unprogrammed state) or is unaffected by ionizing radiation (programmed state). |
| Laser Engery Limitations for Buried Metal Cuts | "Laser Energy Limitation for Buried Metal Cuts Abstract Redundancy by laser cutting of polysilicon fuses has been used by the memory industry for many years. As the levels of metalization layers increases, it becomes more difficult and expensive to delete buried polysilicon lines. Ideally, metal fuses will be cut exclusively. However, to achieve reliable metal line cutting, a wide process window has to be found that can cut metal lines buried beneath the passivation layers. The upper energy limit has previously been thought to result from excess laser energy absorbed by the substrate. We show that another failure mode exists at energies far below the threshold to cause substrate damage directly. The same laser pulse which ejects the passivation and removes the metal is also likely to crack the dielectric material below the metal. Molten metal then fills the crack and maintains an electrical short circuit, preventing the line from being disconnected. |
| Book Chapter | BOOK CHAPTER from LIA Handbook Describes laser make link technology in both lateral and vertical; useful for programmable substrates. |
| Vertical Laser Links | Laser Formed Metallic Connections Abstract Solid metallic connections have been successfully formed between two standard levels of metalization using a focussed IR laser. This new process of laser formed connections has been used to link continuous chains and with resistances of less than 0.8ohm per connection. A commercial laser repair system used extensively by the memory industry was employed to perform approximately 50,000 individual links without failure. The electromigration resistance is comparable to standard metal interconnect. This technology has the potential to replace laser fuse cutting techniques to implement repair schemes and it can be used to program wiring in MCM-D or wafer scale integration applications implemented on silicon substrates. Furthermore, because it is an additive process, it lends itself to redundancy for higher yield and reliability. |
Initial
Radiation Report on the Chip Express CX2001
Heavy Ion Results on FPGAs (Version 2)
Preliminary
Evaluation of the Chip Express QYH580
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