NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

2005 MAPLD International Conference

Ronald Reagan Building and International Trade Center
Washington, D.C.

September 7-9, 2005

Session A. Applications: Military & Aerospace I
(Wednesday morning, September 7)

Session Chairs:
Tanya Vladimirova, University of Surrey
Hans Tiggeler
John Lewis, Federal Aviation Administration

9:00 AM "Welcome to MAPLD"
Richard B. Katz, NASA Office of Logic Design

9:15 AM Submission 107
Welcome and Opening Remarks - "NESC – Safety and Mission Success through Engineering Excellence"
Ralph R. Roe
NASA Engineering and Safety Center
Presentation: roe_p.ppt

9:50 AM
Submission 220
"An FPGA Based Processor for Hubble Space Telescope Autonomous Docking – a Case Study"
Jonathan F. Feifarek and Timothy C. Gallagher
Lockheed Martin Space Systems Company
Abstract: feifarek_a.html
Presentation: feifarek_p.ppt, feifarek_p_bw.ppt
Paper: feifarek_paper.doc

10:15 AM BREAK in the Atrium Ballroom

10:50 AM
Submission 140
"On the Use of Reconfigurable Hardware in Sensor System Integration for Airliner Cabin Environment Research"
Sin Ming Loo
FAA Center of Excellence for Airliner Cabin Environment Research
Boise State University
Abstract: loo_a.html
Presentation: loo_p.ppt
Paper: loo_paper.doc, loo_paper.pdf

11:15 AM
Submission 162
"Development of the Malleable Signal Processor (MSP) for the Roadrunner On-Board Processing Experiment (ROPE) on the Tacsat-2 Spacecraft"
R.L. Coxe¹, G.H. Romero¹, A. Pakyari¹, S.D. Chang¹, G.E. Galica¹, J.M. Glynn¹, B.D. Green¹, M. Leary², J. Lyke³, and D. Fronterhouse⁴¹Physical Sciences Inc.
²Newgrange Design Inc.³AFRL/VSSE⁴Scientific Simulations Inc.
Abstract: coxe_a.html
Presentation: coxe_p.ppt
Paper: coxe_paper.doc

11:40 AM Submission 208
"Radiation Tolerant Intelligent Memory Stack (RTIMS)"
Tak-kwong Ng and Jeffrey A. Herath
NASA Langley Research Center
Abstract: ng_a.html
Presentation: ng_p.ppt

12:05 AM Submission 1027
"FPGA design using the LEON3 Fault Tolerant Processor Core"
Jiri Gaisler and Sandi Habinc, Gaisler Research AB
Presentation: gaisler_s.ppt

12:25 PM
Lunch In The Atrium Ballroom - Asian Adventure

2005 MAPLD International Conference Home Page

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Last Revised: February 03, 2010
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