NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Waveforms: LOLA Digital Unit Flight Unit

Date: October 4, 2007

Waveforms from RTAX2000S unless otherwise noted.

C&T Board

Address line from memory controller.  High slew.

Data line from memory controller.  High slew.

DMA-ACK line from DMAINF, between to FPGAs.  High slew.

RAMACK.  Low slew.

Output enable.  High slew.

Write enable.  High slew.

20 MHz Clock, Input Side of Buffer

Input to 54AC132 from other board, with series termination (100 ohm)

20 MHz Clock, Output Side of Buffer

Output of 54ACS132.

Pulses into the LVDS Drivers on RMU Board.

Channels 0-5, four pictures each (stop1, stop2, with Phases A and B)

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Last Revised: February 03, 2010
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