NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Reliable Digital Electronics Workshop:
Devices, Environments, Design, and Verification

The NASA Office of Logic Design (OLD) has a charter to study the problems of digital engineering for space flight systems and solve them and disseminate the results of our work.  This is very much in the spirit of NACA and forms the foundation of our work.  The web site is part of our output; in particular, the Design Guidelines and Criteria for Space Flight Digital Electronics is a first phase of providing guidelines for our missions and the criteria by which they are judged.  This workshop continues the effort in the development and publishing of these guidelines and criteria.

Early in 2005 NASA OLD will sponsor the first workshop on the reliable design of digital electronics, to be held at the NASA Goddard Space Flight Center in Greenbelt, Maryland.  This session will focus on FPGAs, ASICs, and non-volatile memories.  Items to be discussed include:

Discussions will be informal and can range from data sets, test methods, identification of issues, specific methodologies, etc.  This workshop is targeted to NASA aerospace applications.  Department of Defense, other government agencies, universities, and commercial aerospace engineers are also welcome.  If you wish to discuss a presentation or propose a specific topic to be discussed, please contact me.

Best regards,

Richard B. Katz
NASA Office of Logic Design


In one sense digital electronics design has not changed very much over the past 40 years.

Indeed, much as the designers of the Apollo Guidance Computer designed their CPU with a single logic function (a three-input NOR) logic designers of today use arrays of gates or modules.  Similarly, we have memories with similar characteristics of volatility, stability, and permanence.  The sheer size of our designs has changed from thousands of gates to millions.  This is not a fundamental logic change but it has changed the manner in which we design and verify the solutions.  Similarly, the technologies have changed from a few gates per chip to millions with the speeds and pin counts increasing while the dimensions of the chips continue to shrink in size very year.  This leads to issues in signal and power integrity and radiation sensitivity.

One trend in the industry is to have the logic designs performed by a machine known as the logic synthesizer.  This abstraction often results in the engineer never seeing the logic design and makes the verification task challenging.  This is a fundamental change and a challenge.

Another fundamental change over the past decade is that the job of the integrated circuit manufacturer and the logic designer are no longer disjoint.  Previously, the designer would configure his circuit board with fixed function ICs from standard SSI, MSI, and LSI families or large standard VLSI functions such as microprocessors or bit-slice components, tested and verified by the manufacturer.  Today the integrated circuit design is partially performed by the manufacturer and is completed by the end user.  This splits the design, analysis, and verification tasks between two organizations who essentially work separately.  I shall give two brief examples of issues to demonstrate this.  On the electrical side, the clock skew within a 4-bit 54HC161 binary counter would not be of concern to the logic designer; in an FPGA the designer does have to worry about such matters.  On the environmental side, the logic designer may employ structures built in a triple modular redundant configuration enhancing the radiation tolerance of the supplied microcircuit.

Chip design for space flight missions is now a joint process between the manufacturer and the end user.  And in most cases they do not perform the design, analysis, and verification as a team.  One of the goals of this workshop is to address this issue such that reliable hardware designs are produced.

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Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz