NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Use of Spare Logic Resources


Whether designing digital logic at the board level or when designing an application specific circuit that is implemented in a gate array, designers should leave "margin."  These extra logic resources include gates, flip-flops, RAM blocks, input/output cells, and other resources as applicable to the circuit technology being used.

These resources enable logic device designers to readily respond to changing requirements, fix design errors, enable freedom to trade off resources and power and speed, as well as easing the routing of the chip.

At the end of the project, however, this margin or reserve serves no useful purpose and they are going to be in the embedded system.  This application note will suggest two ways in which these resources can be effectively used.


Traditionally, aerospace logic designers have provided for a number of "test points" that are buffered and brought out of the box to either a subsystem or system test connector.  All such signals should be properly buffered to ensure that any faults induced either through handling or test component failure cannot reasonably effect the reliability of the flight system and that there is reasonable signal quality.

An example from a recent flight design is shown below in Figure 1 where six points are provided.  The buffering is done via a single hex inverter chip.  The only use of the hex inverter integrated circuit is for test points to decouple the test function from the flight hardware.

Figure 1. A Buffered Test Port

Typically, the signals to be brought out of the system are simply wired to one of the buffers.  That works well but with the use of the spare logic resources, the test port can be made more useful for functions such as system debug, improving system testability via making more signals visible at the box level, and providing an aid for calibration in certain system.

The n-bit test port can be made programmable via a simple register load command to the subsystem, allowing related sets of signals to be made visible, allowing for timing verification, capture by a logic analyzer, or other use as appropriate to the subsystem under test. 

For example, in a recently designed system, an eight bit command "programs" the test port to make visible 1 of up to 256 sets of six signals.  The power-on reset signal initializes the test port to provide a "look and feel" of a traditional system, with the six most commonly used signals available on the test port for use by the system test engineers.

The following VHDL code snippet shows the idea.  The eight-bit signal "k_probe" is initialized to "00000000" upon the application of power and is writable through the command interface.  For this system, signals "test1" and "test6" had fixed assignments to critical timing signals for use by the system-level test equipment.

test1 <= ping;
test6 <= time_zero;

k_probe_proc: process (k_probe, fire, cycle_reset, tdc_phase_out, ... )
case k_probe is
   when x"00" =>  test2 <= clk_1mhz;          test3 <= range_gate;
                  test4 <= earth_range_gate;  test5 <= fire;
   when x"01" =>  test2 <= tdc_phase_in( 0);  test3 <= tdc_phase_in ( 1);
                  test4 <= tdc_phase_in( 2);  test5 <= tdc_phase_in ( 3);
   when x"02" =>  test2 <= tdc_phase_in( 4);  test3 <= tdc_phase_in ( 5);
                  test4 <= tdc_phase_in(6);   test5 <= tdc_phase_in(7);


   when others => test2 <= fire;              test3 <= cycle_reset;
                  test4 <= range_gate;        test5 <= earth_range_gate;
   end case;
end process k_probe_proc;


Board Level Logic

Prior to the widespread use of gate array technologies, logic designs were implemented primarily with SSI and MSI devices along with some fixed function LSI components.  Designers would traditionally leave a number of spare logic gates and flip-flops on the board along with some empty component footprints for 14, 16, and 20-pin devices.  This allowed changes for a variety of reasons to be made without having to make new printed circuit boards.

Spare pins, gates, and flip-flops are often available in designers gate arrays.  By allocating these spare logic resources to spare I/O pins the designer can provide "spares" that play an analogous role to that in the discrete designs of previous generations.  This use of spares can save "respinning" an application specific integrated circuit with circuit changes in some cases made with the addition of just a few wires.  Of course, unused inputs should be properly terminated on the board.

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Last Revised: February 03, 2010
Web Grunt: Richard Katz