NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

TTL Design Checklist1

  1. Only gates from the same package should be connected in parallel.

  2. Take note not to exceed fan-out limit (maximum number of circuits fed input signals from a single output terminal).

  3. Check pin compatibility when using devices from different families or manufacturers.

  4. Check manufacturer interchangeability for minor functional differences.

  5. Maintain equal loading in ac and dc terms on multiple output devices with internal feedback.

  6. The dynamic threshold of low-power schottky (LS) gates varies between 1.1 V and 1.4 V depending on circuit configuration; therefore, slow rise times (greater than 50 nanoseconds) will possibly cause pattern sensitivity.

  7. Gates with outputs driving transmission lines should be situated close to the board periphery.

  8. Consider full-range temperature effects on switching characteristics relative to design application.

  9. Use pull-up resistors on devices with open collector gates.

  10. Consider the frequency dependency of power dissipation when the operating frequency is greater than 1 to 2 MHz.

  11. If decoded outputs from counters, particularly from ripple counters, are being used as clocks to drive counters or memory devices, the decoded outputs of interest should be examined for multiple pulses at counter transitions that might ambiguously operate the driven counters or memory devices, and corrective measures should be taken to non-ambiguously operate the driven circuits.

  12. Take note that low-power, low-power Schottky, and Schottky TTL circuits are known to fail when exposed to 5 microjoules or more of electrostatic discharge (ESD) energy.

  13. Consider "current dumping" effects when a multiple input gate is terminated to a single high impedance source such as a 150-ohm line.

  14. All unused input pins should be tied to high- or low-logic levels, depending on the circuit application.  When devices approaching their maximum speed for TTL are used, unused inputs should be "commoned" to used inputs rather than tied high; whereas for low-power Schottky devices with diode inputs, the unused ones can be directly connected to VCC.

  15. Provide isolation for test points so that any foreseeable occurrence, such as shorting between, grounding or external excitation at the test points will not disrupt operational use of the circuit being monitored by the test points.

  16. Consider potential problems involving the use of multiple flip-flops controlled by one or more asynchronous output.

  17. Check interfacing parameters (fan-out, loading, and threshold) when using devices from different families.


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Last Revised: February 03, 2010
Digital Engineering Institute
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