NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Memory Design Checklist1

  1. Avoid using parts at their maximum supply voltage tolerance and/or at their maximum speed. In a large memory system, noise, loading, and skew problems result in reduced apparent working area and reduced effective speed.
  2. Consider carefully the difficulty in "second sourcing" with memory components, since they are far more complex than standard medium scale integration components (MSI); and very few, if any, have identical replacements.
  3. Avoid mixing several technologies within the same memory system. If this is done great care must be taken to ensure that at no time are the pins of any memory component pulled beyond the component's substrate voltage.
  4. When read-only memories (ROM's) are used to replace wired logic gates, the outputs may show noise or extra transitions, since the ROM is not guaranteed to give a single output transition for a single input transition.
  5. In the use of nichrome fused bipolar programmable read-only memories (PROM's) there has been evidence of fuses growing back after programming and of unblown fuses being subject to decay. Ensure that special freezeout tests and high voltage stressing have been carried out, and also consider the greatly delayed production cycles involved.
  6. Take note when using PROM's that the programming operation on devices from the same family are not necessarily compatible. Examples are the 1602 and 1702 devices in which the programming operation forces "ones" to "zeros," and the 1602A and 1702A devices which force "zeros" to "ones."
  7. Caution must be taken when using common bus lines not to allow more than one device to be enabled at a time. System noise and incorrect data problems could result, and depending on output drive capability, physical damage to the device could occur.
  8. In order to minimize transmission line problems, the driver elements should be located as closely as possible to the memory elements, keeping the connecting printed circuit lines as short as possible.
  9. Asynchronous input signals applied to a ROM should be permitted to change within an access time sufficient to meet setup and hold times, prior to clocking the output register. If this does not occur the contents of the output register may be completely unpredictable.
  10. Periodically check PROM programming electrical specifications, since manufacturers often change their recommended programming method to improve programming yields.
  11. Ensure the correct programming conditions (voltage, duration, etc.) when programming PROM's.
  12. Ensure that shift register drivers have sufficient dumping capabilities, otherwise positive or negative spikes may be coupled from one clock to the opposite phase. Spikes may reach over the substrate voltage and activate parasitic substrated transistors and destroy data.
  13. Memory products usually dissipate power at significantly higher levels per package than most large-scale integration (LSI) and MSI components. It is therefore very important that adequate cooling arrangements be made, because the power dissipation per unit area can approach an order of magnitude greater than ordinary TTL.
  14. Allow in the design for the ROM/PROM access time differences from various parts of the array. Differences of four to one have been found for various address locations.
  15. Take caution when using dynamic MOS shift registers (SR's) as low-speed power-saving circuits, since data can be lost if the SR clock speed is reduced instantaneously. The lower frequency limit applies only at high ambient temperatures and not at self-heated high-junction temperatures produced at high clock frequencies.
  16. Take note that when using floating gate metal oxide semiconductor (MOS) PROM's, bit loss occurs under xray and nuclear radiation. In addition, problems of inadequate erasure due to poorly calibrated ultraviolet sources can arise.
  17. Take caution when using MOS electrically alterable PROM's, since data loss can occur from cells subjected to greater than 10 accesses. Given an access time of 1 microsecond, the data could be lost within an hour if 9 continuous reads are made from one location.
  18. Power supply slew characteristics should be evaluated carefully. Two separate problems have been noted. One problem is that at switch-on, a slowly rising power supply may not initialize the random access memory (RAM) logic correctly so that a subsequent initializing procedure is required. Another problem is that sharp, small supply voltage changes that occur in normal memory system operation can cause data loss in some supplier dynamic memory products.
  19. Operating temperatures have to be considered very carefully. Because of their complexity, memory components tend to be more sensitive to temperature extremes than other types of devices.
  20. Consider that large MOS memory systems often require error correction and detection (the inclusion of "Hamming" error correction codes in the design). This approach improves the effective system reliability by two orders of magnitude, and the associated error indicators simplify scheduled maintenance.
  21. Consider access time measurement criteria carefully. While some manufacturers measure access times to the VOH and VOL voltage levels, others measure access to the 1.5 voltage level for both high- and low-level outputs. Additionally, some suppliers specify two output loads in their dc characteristics, but measure access time against one output load.
  22. Many dynamic RAM's require a substrate bias supply (VBB) to ensure correct operation. Unless this bias supply is raised before the main supply and dropped after the main supply, high currents may be drawn. Also, if the bias supply is reversed even in a transient mode, the parasitic substrate transistor will draw extremely high currents. Since the internal capacitances of the RAM are terminated to the substrate, very good transient bypassing is required.
  23. Take care when using bipolar memory devices (e.g., many ROM/PROM devices) with PNP transistor lowpower Schottky style inputs. It is important that the inputs not be pulled below ground until the PNP device is saturated; otherwise, very long access times will be observed.
  24. Allow for input/output coupling features of static RAM's in the system design. Although possibly not shown on the write- cycle data published by the manufacturers, the input data may appear on the output during the write mode.

1From PREFERRED RELIABILITY PRACTICES, GUIDELINE NO. GD-ED-2203, DESIGN CHECKLISTS FOR MICROCIRCUITS, JOHNSON SPACE CENTER

Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal