NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

CMOS Design Checklist1

  1. Allow for hold-time and setup-time requirements of CMOS flip-flops, registers, and latches. Inputs to CMOS devices must be stable before and remain stable even after the active clock pulse edge.

  2. Take adequate precautions to avoid ESD damage.

  3. Account for possible incompatibilities with similar part numbers from different manufacturers when establishing parts lists.

  4. Investigate the package choice/reliability tradeoff for each design application.

  5. When using single-stage (unbuffered) multiple-input CMOS devices, consider that both dynamic and static performance of these circuits can deteriorate under certain logic conditions to the extent that logic systems display pattern sensitivity.

  6. Protect signal inputs against overvoltage spikes and input currents exceeding ratings, i.e. many CMOS devices have ten milliamperes as the maximum allowable input current. Consider that if the overvoltage spike is greater than the supply voltage, the parasitic PNP or NPN transistors become forward biased and latch-up can occur.

  7. Excessive current through switches results in latching and destructive breakdown; therefore, protective circuitry is essential.

  8. Consider the noise margin when using 5-volt supply levels. CMOS has an order of magnitude less energy noise margin than TTL (approximately 0.4 nanojoules for CMOS and 4.0 nanojoules for standard TTL).

  9. The power supply should switch on by itself first before signal inputs are applied, since damage may occur if the diode between input and VDD is forward biased.

  10. Slowly rising or falling input signals can lead to multiple triggering, particularly if the supply voltage is poorly regulated, and also to higher supply (IDD) currents.

  11. Maximum power dissipation of the device could be exceeded if input rise and fall times are greater than 15 microseconds, (depending on device type) especially using high current drivers with high supply voltages.

  12. Terminate all unused inputs; a floating input can turn a CMOS device on, causing faulty operation and possible damage, and also uses increased power since both p- and n-transistors are partially conducting.

  13. Ensure that interfacing parameters between CMOS and other logic families are correct, particularly with regard to loading and thresholds.

  14. Keep interconnections short or use terminations, as long interconnections in high speed systems behave like transmission lines, which can cause reflections and ringing.

  15. Do not use CMOS gates as linear amplifiers; this can destroy buffer gates, cause failure of the device to operate below 4 volts, and make supplier interchangeability even more problematical.

  16. Avoid long, closely spaced, parallel traces on PCB's to minimize crosstalk.

  17. Flip-flops with transmission gate inputs are particularly prone to malfunction if the inputs are driven above and below the supply voltages. This can occur when interfacing from other logic families and from distant boards.

  18. Try not to design to typical values because of the large part-to-part process variations. In many cases guaranteed values are several orders of magnitude larger than typical values.

  19. Reduce ground/power supply inductance (power/ground planes) and use sufficient decoupling capacitors, as simultaneous switching of multiple outputs causes noise and voltage drops on power supplies.


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Last Revised: February 03, 2010
Digital Engineering Institute
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