NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

RT54SX72S: Propagation Delay vs. Life

The following chart shows aggregate data from multiple lots of RT54SX72S FPGAs, totalling 1,040 individual devices.  The speed data, with a mean delay of 73.8 ns, is measurements of the binning circuit, which is representative of logic paths and is used in determing device speed grade.  Note that the delays over life do not necessarily "track," as there are both differences in the changes of delay as well as some differences in the sign of a delay change.

Construction of the RTSX-S Binning Circuits

• 5 segmented vertical routing tracks are allocated to the binning column
• Fixed length horizontal tracks
• 3 Fuses per connection
  • Output
  • Cross connect
  • Input
• Number of rows per device
  • RT54SX32S has 30 rows
  • RT54SX72S has 48 rows
• Number of fuses = ((N-1) x 3) + 2
  • RT54SX32S => ((30-1) x 3) + 2 = 89
  • RT54SX72S => ((48-1) x 3) + 2 = 143

Notes:

1. RH1280 Life Test Delta Data
2. RH1280 Life Test Delta Data Graphs

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Last Revised: February 03, 2010
Digital Engineering Institute
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