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A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

PowerPC


Heavy ion SEE test of Virtex4 FPGA XC4VFX60 from Xilinx

Christian Poivey, Melanie Berg, Scott Stansberry, Mark Friendlich, Hak Kim, Dave Petrick, Ken LaBel

Test Date(s): February 16-19, 2007
Report Date: June 28, 2007

 Introduction: This study has been undertaken to determine the single event effect susceptibility of the Xilinx Virtex 4 Field Programmable Gate Array (FPGA) XC4VFX60. Device under test (DUT) was monitored for destructive and non destructive events induced by exposing it to a heavy ion beam at the Texas A&M Cyclotron Single Event Effects Test Facility. Test was performed in the frame of HST/RNS project.

Summary: XC4VFX60 Xilinx FPGA is not sensitive to Single Event Latchup up to the maximum tested LET of 58 MeVcm2/mg. SEFI sensitivity is high in comparison with commercial Power PC SEFI cross-sections. External scrub provides a significant improvement. Self-scrub is not very effective. Main reason is its inability to correct MBUs. It is also probable that test flux was too high for self-scrub capability. No other kind of SEFI was observed during these tests. In most cases recovery from SEFI is obtained via reconfiguration and reload of code stored in PPC external memories.


RAD750® 6U CompactPCI extended single-board computer

 

  


RAD750® 3U CompactPCI single-board computer


 

  


RAD750TM SPACEWIRE-ENABLED FLIGHT COMPUTER FOR LUNAR RECONNAISSANCE ORBITER

International Spacewire Conference 2007

 

 Abstract (partial): An additional version of the RAD750TM CompactPCI® 6U radiation hardened single board computer has been developed and delivered for use on the Lunar Reconnaissance Orbiter (LRO) mission developed by NASA Goddard Flight Center, scheduled to launch in late 2008 as the first mission in preparation for manned missions to the Lunar surface. This new variant of the RAD750 processor incorporates both a SpaceWire router and 1553 interface. The LRO mission processor architecture represents a hybrid implementation in which the SpaceWire links, 1553 bus, and PCI bus are all utilized to interconnect the flight computer and on-board instruments. The RAD750 computer includes 36 MB of radiation hardened SRAM, 4 MB of non-volatile memory, and the ability to support PROM or EEPROM in its SUROM locations. The computer also includes an additional 8 MB of radiation hardened SRAM dedicated to supporting the SpaceWire ASIC that provides a four port router through a PCI interface. The 1553 interface consists of an Actel FPGA, Aeroflex “SμMMIT DXE” ASIC, and dedicated memory. SpaceWire transport layer software was developed for the embedded microcontroller that resides on the SpaceWire ASIC using a C compiler developed by BAE Systems.


MRO Spaceflight Computer Side Swap Anomalies [Export Version]

Public Lessons Learned Entry: 2041
Lesson Date: December 16, 2008

 Abstract: A few months into its mission, MRO began experiencing unexpected side swaps to the redundant flight computer that placed the spacecraft into safe mode. The problem was traced to subtle inconsistencies between the MRO design implementation of an ASIC device and a known limitation of that device. Users of the RAD750 spaceflight computer should assure that the "PPCI Erratum 24" ASIC defect cannot cause excessive accumulation of uncorrectable SDRAM memory errors, and that the system architecture has robust error recovery capabilities.


Xilinx Virtex-II Pro PowerPC Proton Test Results

David Petrick and Dr. James Howard

 Introduction
This proton test was performed on multiple XQ2VP40 devices, a dual processor version of the Virtex-II Pro with an epitaxial layer. The XQ2VP40 device was tested using the XRTC board specifically designed for radiation testing of the Virtex-II Pro. Testing was conducted at the Indiana University Cyclotron Facility (IUCF).  This report outlines the test setup, design applications, static results for the registers and cache, and various results from executing a dynamic application on the PowerPC.


PC603E 32-Bit RISC µP Radiation Effects StudyXL

P.T. McDonald, W.J. Stapor, and B.G. Henson
Innovative Concepts Incorporated
archive

 ABSTRACT
Advanced high performance microprocessors, especially reduced instruction set, or RISC, are highly desired in the design and implementation of aerospace applications. Limited radiation effects measurement data exists for many current generation commercial microprocessor products. We performed single event effects (SEE) and total dose (TID) proton measurements on a RISC µP, the Motorola PowerPC 603e microprocessor. The data are used estimate event rates in typical environments, including a unique application of the PROFIT1 model to estimate heavy ion response.


Analyzing the Xilinx Virtex-II Pro PowerPC using the Dhrystone Benchmark Application

David Petrick
NASA – Goddard Space Flight Center

 Introduction
   The Xilinx Virtex-II Pro FPGA is available with one or two PowerPC405 processor cores embedded within the FPGA fabric.  The Dhrystone benchmark application is used to test processor performance and how well a compiler optimizes the code. The performance is measured in Dhrystone MIPS, or DMIPS. Similar work was done by Xilinx (Application Note 507), which reports that the PowerPC produces 600+ DMIPS at 400 MHz. However, these results were obtained by using the WindRiver Diab DCC 5.2 compiler, not the compiler supplied with Xilinx’s Embedded Development Kit (EDK). This report lists the DMIPS results using the GNU-GCC 3.4 compiler and shows how varying the bus frequency, processor frequency, and compiler settings affect the DMIPS performance. It also describes the performance variations between commercial devices, speed grades, and the left and right processors.
RAD750 HomeXL Some links dead, removed or changed by BAE Systems and can't find a replacement link.  Let me know if you can find them.  I have fixed some of them (1/7/2006) after one engineer wrote in with some corrections.  
RAD 6000 Home

RAD6000 Technical LibraryXL


A Processor Solution for the Second Century of Powered Space Flight

J. Marshall and R. Berger
Digital Avionics Systems Conferences, 2000. Proceedings. DASC. The 19th ,Volume: 2 , 7-13 Oct. 2000, Pages:8.A.2_1 - 8.A.2_8 processor_solution_marshall.pdf

 Introduction
Lockheed Martin Space Electronics & Communications in Manassas, Virginia begins the new millennium with a family of space processors that may be used incrementally by applications over the coming years.  Today's established RAD6000™ and this year's RAD750™ provide users with growth potential in processing and clear paths that prevent obsolescence through the use of industry standards and the leveraging of COTS products in processors, tools, interfaces and test equipment.


The RAD750™ - A Radiation Hardened PowerPC™ Processor for High Performance Spaceborne Applications

R. Berger, D. Bayles, R. Borwn, S. Doyle, A. Kazemzadeh, K. Knowles, D. Moser, J. Rodgers, B. Saari, and D. Stanley
BAE Systems
IEEE Aerospace Conference, 2001
IEEE Proceedings. ,Volume: 5 , 10-17 March 2001, Pages:2263 - 2272 vol.5
rad750_2001_berger.pdf

 Abstract
BAE SYSTEMS has developed the RAD750™, a fully licensed radiation hardened implementation of the PowerPC 750™ microprocessor, based on the original design database. The processor is implemented in a 2.5 volt, 0.25 micron, six-layer metal CMOS technology. Employing a superscalar RISC architecture, processor performance of 240 million Dhrystone 2.1 instructions per second (MIPS) at 133 MHz is provided, while dissipating less than six watts of power. The RAD750 achieves radiation hardness of 1E-11 upsets/bit-day and is designed for use in high performance spaceborne applications. A new companion ASIC, the Power PCI, provides the bridge between the RAD750, the 33 MHz PCI backplane bus, and system memory. The Power PCI is implemented in a 3.3 volt, 0.5 micron, five-layer metal CMOS technology, and achieves radiation hardness of <1E-10 upsets/bit-day. This paper describes the implementation of both designs.

ISC (Integrated Spacecraft Computer) Case Study of a Proven, Viable Approach to Using COTS in Spaceborne Computer Systems

Doyle Lahti, Gary Grisbeck, and Phil Bolton
General Dynamics Information Systems

14th Annual/USU Conference on Small Satellites

scc00-iv-4.pdf

Abstract
By judiciously using COTS technology a new space computer product that has lower cost, higher performance, is easy to use and retains the high reliability necessary for use in spaceborne missions was developed.  Modern COTS processors and memories are used with a mixture of military and radhard components to meet the unique thermal-mechanical environment and radiation environment of space and still satisfy the need for high-reliability, low power consumption and low weight.


Backside Device Irradiation for Single Event Upset Tests of Advanced Devices

Gary M. Swift
JPL/California Institute of Technology

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002

swift_thin_seesymp02.ppt

Tales from the Cave

  • Texas A&M Wishlist:
    • Upstream Degrader (for uniformity)
    • LET and/or Energy Spectrum Detector
  • Backside thinning is NOT so easy
    • Yield Problems
    • Need Long-Range Ions
  • Backside Irradiation Requires Careful LET Assignments

Examples include SDRAMs and the Power PC (May 7, 2002)


Single-Event Upset in the PowerPC7400 (G4) Microprocessor

F. Irom, G. M. Swift, F. Farmanesh, Jet Propulsion Laboratory; D. G. Millward, Millward Research

 

 Abstract
Proton and heavy-ion single-event upset susceptibility has been measured for the Motorola PowePC7400. The results show that this advanced device has low upset susceptibility, despite the scaling and design advances.


Single-Event Upset in Evolving Commercial Silicon-on-Insulator Microprocessor Technologies

F. Irom, F.H. Farmanesh, G.M. Swift, A.H. Johnston, and G. L. Yoder
irom_2006.doc
NSREC 2003

 Abstract
Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and D-cahe were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors is discussed.


Validation of an SEU Simulation Technique for a Complex Processor: PowerPC7400 G4 Microprocessor

S. Rezgui, R. Velazco, TIMA; G. M. Swift, Jet Propulsion Laboratory

Presented at the 2002 IEEE NSREC
Phoenix, AZ

 Abstract
A methodology for error rate prediction of a complex processor running applications by a software-based fault injection technique is presented. The methodology is validated through comparison with heavy ion data obtained on advanced Power PC processors.


Radiation Hardened PowerPC 603e ™ Based Single Board Computer

Gary R. Brown
Honeywell Inc.
(727) 539-3705
gary.r.brown@honeywell.com

IEEE Aerospace Conference, 2001

 Abstract
The RHPPC Single Board Computer (SBC) has an open architecture based on COTS standards for form factor, instruction set, operating system, backplane bus, and I/O. The RHPPC is a radiation hardened processor derived from PowerPC 603e™ technology licensed from Motorola.  The RHPPC is 100% software compatible with the commercial PowerPC603e™ part allowing all the mature COTS PowerPC™ software development tools to be used with the RHPPC. The RHPPC SBC architecture has been defined in conjunction with several key users.

The RHPPC SBC has features and capabilities that enable systems to provide capabilities never before possible. The RHPPC SBC enables mission processing to be performed on the satellite that in turns allows the satellite to downlink information directly to users.

The SBC generates 210 DMIPS while dissipating 12.5 W (nom) for almost 17 MIPS/W. The form factor is 6U x 220 which is the COTS standard. Additionally, the design allows for two COTS compatible PCI Mezzanine Cards (PMC) like daughter board slots. The RHPPC SBC is designed to withstand the stressing vibration environment of launch, and the radiation and thermal environments of space. The design is very reliable with a predicted reliability of better than 0.99 for 15 years with a cold spare. The SBC SEU rate is 1 every 62 years in a constant Adams 90% worst case GEO environment.

The RHPPC SBC also provides three types of standard serial I/O. There is a MIL-STD-1553B port with a 8K x 16 buffer memory. The 1553 port is upgradable to dual rate AS1773 with a minor board layout change. There are two full duplex 8250 (UART) compatible asynchronous ports. And there are two full duplex synchronous serial ports.

The RHPPC has a VxWorks™ integrated operating environment consisting of startup code (SUROM), a Board Support Package (BSP) and I/O drivers. This flight code is written in C using Wind River's COTS Tornado™ software development environment.

Table of Contents

1. Introduction
2. Single Board Computer Overview
3. RHPPC SBC Feature Summary
4. Processor Enhancement Component (PEC)
5. Clocks
6. Local Mezzanine PCI Bus
7. SBC Performance
8. RHPPC Processor
9. Level 2 (L2) Cache
10. Memory
11. CPCI Backplance Bus
12. Input/Output
13. Timers
14. Interrupts
15. Power
16. Mechanical
17. Radiation Hardness
18. Reliability
19. Software Development


RAD6000 Computer Boards

NASA Advisory NA-MSFC-06-01
January 12, 2006.

  

1formerly Lockheed-Martin formerly Loral formerly IBM Federal Systems

Applications of Power PC.  These references do not focus on the processor.

Radiation Test Report: Universal Mini Controller (CPU Card and Power Supplies)

Engineering Directorate
Avionics Systems Division
December, 1999
JSC 28873

28873.pdf

Note: The CPU tested in this report is the 603e.

 Introduction
Candidate elements of the Universal Mini Controller (UMC) were tested at the Indiana University Cyclotron Facility (IUCF) to assess susceptibility of the unit to high-energy ionizing radiation. There are no current implementations of the UMC; however, the system is being looked at for use in the TransHab and Mars projects, as well as Orbiter upgrades. The test was conducted on November 12, 1999, with all test results provided in this report.

Conclusions
Each position of all units tested received a minimum fluence of 1E10 protons/cm2, which is equivalent to a TID of 600 rads(Si). No degradation in performance due to the TID was noted. All test articles were operational at the end of the test.

  • The MTBF for the UMC CPU Single Event Upset is 1.63 years and the MTBF for the UMC CPU Functional Interrupt recovering automatically is 0.61 years.
  • Neither UMC PS1 nor UMC PS2 had any failures from radiation testing.

The total MTBF for both the UMC Single Event Upset and Functional Interrupt recovering automatically is 1.63 years with the internal cache disabled, and 0.44 years with the internal cache enabled.


STATUS OF CHIPS: A NASA UNIVERSITY EXPLORER ASTRONOMY MISSION

Will Marchant1 and Dr. Ellen Riddle Taylor2
1Space Sciences Laboratory - UC Berkeley
2DesignNet Engineering Group

14th Annual/USU Conference on Small Satellites

v-6.pdf

 Abstract
In the age of "Faster, Better, Cheaper", NASA's Goddard Space Flight Center has been looking for a way to implement university based world class science missions for significantly less money. The University Explorer (UNEX) program is the result. UNEX missions are designed for rapid turnaround with fixed budgets in the $10 million US dollar range. The CHIPS project was selected in 1998. The CHIPS mission has passed the Concept Study and will be having the Confirmation Review in August 2000. Many lessons have already been learned from the CHIPS UNEX project. This paper will discuss the early issues surrounding the use of commercial satellite constellations as the bus and the politics of small satellites using foreign launchers. The difficulties of finding a spacecraft in the UNEX price range will be highlighted. The advantages of utilizing Internet technologies from the earliest phases of the project through to communications with the spacecraft on orbit will be discussed. The current state of the program will be summarized and the project's plans for the future will be charted.

[Note: This used the PowerPC 750 and a TCP/IP stack]

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