NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Spaceborne Processor and Avionics Papers


Title, Authors, Reference Abstract

Accelerated Verification of Digital Devices Using VHDLXL

Sandi Habinc and Peter Sinander
European Space Agency

This paper presents two aspects for improving the verification of microprocessors; program-less verification, and methods for handling large differences in abstraction level between a reference model and the actual design. Program-less verification is a type of pseudo random verification where the notion of a software program executing on the microprocessor has been abandoned.

The Problem with Aviation COTS

Lionel D. Alford, Jr. USAF
IEEE AESS Systems Magazine
February 2001, pp. 33-37


Commercial Off the Shelf (COTS) has become a byword for acquisition reform, but there are significant risks associated with the use of COTS products in military systems.  This paper explains how COTS can negatively affect military acquisitions and gives ideas on how to plan and resolve COTS caused problems.

A Study of Flight-Critical Computer System Recovery from Space Radiation-Induced Error

Chung-Yu Liu
IEEE AESS Systems Magazine
September 2002, pp. 19-25


It is well known that space radiation, containing energetic particles such as protons and ions, can cause anomalies in digital avionics onboard satellites, spacecraft, and aerial vehicles flying at high altitude. Semiconductor devices embedded in these applications become more sensitive to space radiation as the features shrink in size. One of the adverse effects of space radiation on avionics is a transient error known as single event upset (SEU). Given that it is caused by bit-flips in computer memory, SEU does not result in a damaged device. However, the SEU induced data error propagates through the run-time operational flight program, causing erroneous outputs from a flight-critical computer system.

This study was motivated by a need for a cost-effective solution to keep flight-critical computers functioning after SEU occurs. The result of the study presents an approach to recover flight-critical computer systems from SEU induced error by using an identity observer array. The identity observers replicate the state data of the controller in distinct data partitions. The faulty controller can be recovered by replacing data image of the faulty data Partition with that of the healthy data partition. The methodology of applying such an approach from the fault tolerant control perspective is presented. The approach is currently being tested via computer simulation.

Aging Avionics: The Problems and the Challenges

Ellis Hitt and Bob Zwitch
IEEE AESS Systems Magazine
September 2002, pp. 16-21


Aging avionics have become a problem because aircraft are being kept in service far longer than the original plan. This paper discusses the four key problems of aging avionics: 1) determining the systems that are the high cost drivers in order to select those that should receive priority; 2) determining the requirements for the replacement; 3) identifying alternative technologies that will satisfy the requirements and are affordable; and 4) determining the funding required and acquiring the funding needed to replace the aging avionics. Challenges encountered in solving these problems include management and technical. The problem of aging avionics is not limited to a single aircraft but occurs across all aircraft. Cost-effective modernization requires cutting horizontally across all aging aircrft and coordination with the end users and the existing management structure. A key technical challenge is to select an architecture that is upgradeable since the funding limitations may ensure parts will become obsolete prior to the completion of a drawn-out production.

The Cost of COTS

Jim Hall and Ray Naff
IEEE AESS Systems Magazine
August 2001, pp. 20-24


Fairchild Defense, a division of Orbital Sciences Corporation, has been a pioneer in the use of Commercial-Off-The-Shelf (COTS) hardware, software, and tools in military equipment. Fairchild has developed a cost and schedule effective approach to the use of COTS elements. This paper discusses Fairchild's experience with the use of COTS in military equipment and special considerations imposed because of the military environment.

Airborne Computer Technology

W. T. Chow
IBM Electronics Systems Center
Owego, New York

Proceedings of the Tenth Space Congress
Cocoa Beach, Florida
April 11-13, 1973
pp. 4-19 through 4-28


The development of airborne digital computer has been greatly influenced by rapid technological advances.  This paper provides an overview of the present status and the direction of further evolution.  It discusses the changes that are taking place in the areas of hardware, software, and computer organization; and suggests a number of approaches towards a broadened usage of airborne computer to take advantage of its increasing capability and decreasing cost.

Computers and the Space Program: An Overview

C. C. Kraft, Jr.
IBM Journal of Research and Development
Volume 20, Number 1, Page 3 (1976)


Since the earliest days of the National Aeronautics and Space Administration, the American space program has been dependent on the data processing industry. Without the computer, there would have been no space program and, likewise, without the space program the main technological forces driving the computer industry forward would have been missing.

Development of On-board Space Computer Systems

A. E. Cooper, W. T. Chow
IBM Journal of Research and Development
Volume 20, Number 1, Page 5 (1976)


This paper describes the functions, characteristics, requirements, and design approaches of the on-board computers for seven space vehicles - Saturn I, Orbiting Astronomical Observatory, Gemini, Saturn IB, Saturn V, Skylab, and Space Shuttle. The data contained in this paper represent an encapsulation of sixteen years of space-borne-computer development. In addition, the evolution of computer characteristics such as size, weight, power consumption, computing speed, memory capacity, technology, architectural features, software, and fault-tolerant capabilities, is summarized and analyzed to point out the design trends and the motivating causes. The evolution in utilization of the on-board computers; their interface with sensors, displays, and controls; and their interaction with operators are summarized and analyzed to show the increasing role played by computers in the overall space-vehicle system.

Skylab Attitude Control System

T. R. Coon, J. E. Irby
IBM Journal of Research and Development
Volume 20, Number 1, Page 58 (1976)


The attitude stabilization and control system for Skylab evolved from an analog controller into a fully digital processing system. Features of this system include a software-determined attitude reference to provide general maneuvering ability, an in-orbit programming capability, the use of large control moment gyros for attitude control, and the use of vehicle maneuvers to desaturate gyro momentum. The objectives, requirements, and implementations of the control system software are described, along with the rationales for certain design decisions and discussion of some system dynamics and actual performance.

Achieving Reliability: The Evolution of Redundancy in American Manned Spacecraft Computers

J.E. Tomayko
Wichita State University

Journal of the British Interplanetary Society
Vol. 38, pp. 545-552, 1985


Computers are a key component onboard manned spacecraft.  Gemini, Apollo, Skylab and the Space Shuttle all carried computer systems of increasing functionality and complexity.  All the computer hardware involved in those systems was rated at 95 per cent reliability or better; yet in no case was a computer system implemented without some alternative method of performing critical functions so that crew safety was assured.  How the National Aeronautics and Space Administration (NASA) gained the last five per cent of near total reliability is the story of the evolution of the concept of "backup" to the concept of "redundancy."  Success of this evolution is epitomized by the Shuttle, which did what no manned spacecraft had ever done: carry men on its first test flight.  The main factor in enabling NASA to take such a risk was the redundancy built into the Orbiter.

ISC (Integrated Spacecraft Computer) Case Study of a Proven, Viable Approach to Using COTS in Spaceborne Computer Systems

Doyle Lahti, Gary Grisbeck, and Phil Bolton
General Dynamics Information Systems

14th Annual/USU Conference on Small Satellites


By judiciously using COTS technology a new space computer product that has lower cost, higher performance, is easy to use and retains the high reliability necessary for use in spaceborne missions was developed.  Modern COTS processors and memories are used with a mixture of military and radhard components to meet the unique thermal-mechanical environment and radiation environment of space and still satisfy the need for high-reliability, low power consumption and low weight.

Obsolete Processor Replacement Options

Derek Maddox
Ball Aerospace & Technologies Corporation, Aerospace Systems Division


Background (excerpt)
Processor obsolescence is becoming an increasingly vexing problem for embedded computer users.  From military and civilian aircraft, to manufacturing facilities, to air traffic control facilities, aging computer systems present a variety of problems. Sometimes the problem is diminishing availability of spare parts for computer repair. At other times the problem is the inability of the processor to absorb new requirements because of limited processor throughput or memory. Regardless how the problem manifests itself, a solution, which is often proposed, is to replace the processor with a more modern piece of equipment. This solution certainly answers the problem with hardware, but leaves the question of what to do with the software which the processor runs.

Advanced Microcircuit Emulation (AME) Program – Developing Next Generation Emulation Technology

Harvey M. Hanson, Space and Naval Warfare Systems Center, San Diego, CA; Donald F. O’Brien, Alex Melnikow, Defense Logistics Agency, Ft. Belvoir, VA; James S. Crabbe, Les R. Avery, Sarnoff Corporation, Princeton, NJ


This paper presents the Advanced Microcircuit Emulation (AME) Program, a Defense Logistics Agency (DLA) managed tri-service effort that is developing the next generation of form, fit, and function (FFF) microcircuit emulation capability. This program is operated independently from the Defense Supply Center’s (DSCC) Generalized Emulation of Microcircuits (GEM) Production Program. AME’s technology scope includes advanced digital devices, microprocessors/microcontrollers, memory, analog, hybrids, and assemblies employing AME technologies. The paper begins with a brief review of the program’s background and drivers. It continues by detailing AME’s program structure, current status, and concludes with future plans.

An Error Correction Code to Address Neutron Single Event Upsets in Semiconductor Memory

David W. Jensen, Ph.D.
Advanced Computing Systems
Rockwell Collins

Thirteenth Biennial Single Effects Symposium
Manhattan Beach, CA, April, 2002

Introduction and Summary

  • Why concerned about Neutron Single Event Upsets (NSEUs)?
  • Error correction codes
  • Combining multiple mitigation techniques could enable an NSEU-tolerant, commercially-fabricated microprocessor
  • Presented efficient error correction block code to address Singe Event Upsets (SEUs) and Multiple Bit Upsets (MBUs) in semiconductor memory

Note: Could not make a .pdf file.  (May 3, 2002)

Analysis of the Effects of SEUs on the Hidden Parts of a Pipelined Microprocessor: A Case Study

F. Faure, R. Velazco, TIMA-CMP; M. Violante, M. Rebaudengo, M. Sonza Reorda, Politecnico di Torino

Presented at the 2002 IEEE NSREC
Phoenix, AZ

A method for estimating the sensitivity to transient errors of a pipelined-cached processor when executing a given program is proposed. Preliminary results show good agreement between predicted and measured figures.



Dennis L. Oberg, Member, IEEE, Jerry L. Wert, Eugene Normand, Joseph D. Ness, Peter P. Majewski, and Richard A. Kennerud

Boeing Defense & Space Group
Seattle, WA 98124-2499


This report presents the results of Single Event Effect (SEE) characterization testing of the Intel 87C51FC microcontroller for use in Space Station Freedom (SSF). The 87C51FC exhibited 4 types of SEE: RAM upset and three types of system errors, i.e., reset, latchup, and power cycle (a condition not correctable by the onboard watchdog timer). The microcontroller cross sections and response rates for these single event effects were determined.

The RAD750TM - A Radiation Hardened PowerPCTM Processor for High Performance Spaceborne Applications

R. Berger, D. Bayles, R. Brown, S. Doyle, A. Kazemzadeh, K. Knowles, D. Moser, J. Rodgers, B. Saari, and D. Stanley
BAE Systems, Manassas, VA

Basil Grant
LTS Corporation, Manassas, VA

IEEE Aerospace Conference, 2001

BAE Systems has developed the RAD750TM , a fully licensed radiation hardened implementation of the PowerPC 750TM microprocessor, based on the original design database.  The processor is implemented in a 2.5 volt, 0.25 icron, six-layer metal CMOS technology.  Employing a superscalar RISC architecture, processor performance of 240 million Dhrystone 2.1 instructions per second (MIPS) at 133 MHz is provided, while dissipating less than six watts of power.  The RAD750 achieves radiation hardness of 1E-11 upsets/bit-day and is designed for use in high performance spaceborne applications.  A new companion ASIC, the Power PCI, provides the bridge between the RAD750, the 33 MHz PCI backplane bus, and system memory.  The Power PCI is implemented in a 3.3 volt, 0.5 micron, five-layer metal CMOS technology, and achieves radiation hardness of < 1E-10 upsets/bit-day.  This paper describes the implementation of both designs.

Table of Contents

1. Introduction
2. RAD750 Architecture
3. RAD750 Circuitry
4. RAD750 Design Validation
5. Technology Issues and Test Sites
6. Power PCI Companion ASIC
7. Conclusion

Radiation Hardened PowerPC 603e ™ Based Single Board Computer

Gary R. Brown
Honeywell Inc.
(727) 539-3705

IEEE Aerospace Conference, 2001

The RHPPC Single Board Computer (SBC) has an open architecture based on COTS standards for form factor, instruction set, operating system, backplane bus, and I/O. The RHPPC is a radiation hardened processor derived from PowerPC 603e™ technology licensed from Motorola.  The RHPPC is 100% software compatible with the commercial PowerPC603e™ part allowing all the mature COTS PowerPC™ software development tools to be used with the RHPPC. The RHPPC SBC architecture has been defined in conjunction with several key users.

The RHPPC SBC has features and capabilities that enable systems to provide capabilities never before possible. The RHPPC SBC enables mission processing to be performed on the satellite that in turns allows the satellite to downlink information directly to users.

The SBC generates 210 DMIPS while dissipating 12.5 W (nom) for almost 17 MIPS/W. The form factor is 6U x 220 which is the COTS standard. Additionally, the design allows for two COTS compatible PCI Mezzanine Cards (PMC) like daughter board slots. The RHPPC SBC is designed to withstand the stressing vibration environment of launch, and the radiation and thermal environments of space. The design is very reliable with a predicted reliability of better than 0.99 for 15 years with a cold spare. The SBC SEU rate is 1 every 62 years in a constant Adams 90% worst case GEO environment.

The RHPPC SBC also provides three types of standard serial I/O. There is a MIL-STD-1553B port with a 8K x 16 buffer memory. The 1553 port is upgradable to dual rate AS1773 with a minor board layout change. There are two full duplex 8250 (UART) compatible asynchronous ports. And there are two full duplex synchronous serial ports.

The RHPPC has a VxWorks™ integrated operating environment consisting of startup code (SUROM), a Board Support Package (BSP) and I/O drivers. This flight code is written in C using Wind River's COTS Tornado™ software development environment.

Table of Contents

1. Introduction
2. Single Board Computer Overview
3. RHPPC SBC Feature Summary
4. Processor Enhancement Component (PEC)
5. Clocks
6. Local Mezzanine PCI Bus
7. SBC Performance
8. RHPPC Processor
9. Level 2 (L2) Cache
10. Memory
11. CPCI Backplance Bus
12. Input/Output
13. Timers
14. Interrupts
15. Power
16. Mechanical
17. Radiation Hardness
18. Reliability
19. Software Development

32-bit Radiation-Hardened Computers for Space

IEEE Aerospace Conference [pretty sure]

Captains Joseph Nedeau and Dan King Phillips Laboratory/VTME

Ken Hunt
Phillips Laboratory/VTMI

Denise Lanza
Maxwell Technologies

Lester Byington
The Aerospace Corporation

the past 11 years, the Air Force Research Laboratory (AFRL), Phillips Research Center (formerly Phillips Laboratory) has championed the development of microprocessors and computers for United States Air Force (USAF) space and strategic missile application. The latest of these programs, the Advanced Technology Insertion Module (ATIM), is currently scheduled for completion at the end of 1997. ATM is developing two single-board computers based on 32-bit reduced instruction set computer (RISC) processors. ATIM technology is baselined in the majority of today's Department of Defense (DoD), NASA, including Mars Pathfinder, and commercial satellite systems. The Improved Space Computer Program (ISCP) is envisioned as the next-generation space computer: merging advanced technologies and architectures to meet the high-performance, on-board processing needs for 21st century DoD, NASA, and commercial satellites. ISCP is a three pronged effort to evaluate evolving mission requirements, develop a commercial- heritage architecture, and integrate emerging technologies for space applications. These three areas are: the Phase I Concept/Architecture Studies, the Improved Space Architecture Concept (ISAC), and the technology development efforts. ISAC lays out a sequential approach aimed at developing and demonstrating the potential for on-board, satellite processing. The combined serial and parallel development activities will prove that commercial-heritage architectures and technologies can reduce the development time and costs associated with building the next-generation spacecraft.

LEON-1 Processor - First Evaluation Results


Jiri Gaisler
European Space Research and Technology Centre (ESTEC)

The LEON-1 is a synthesisable processor developed internally at ESTEC/TOS-ES. It has been synthesised targeting both ASIC and FPGA technologies. This paper describes the rational, design goals and current status of the LEON development.

Embedding COTS Processors into Fault Tolerant Space Applications

Joseph R. Marshall, Jr.
Dale Langston
Loral Federal Systems

Paper AIAA-95-1032-CP
A Collection of Technical Papers
AIAA Computing in Aerospace 10

March 28-30, 1995
San Antonio, TX

This paper describes our approach for utilizing Commercial Off The Shelf (COTS) processors in fault tolerant space applications.  The history and fault tolerance requirements of space computers are reviewed.  We discuss the trades that enabled us to fashion a general purpose high performance radiation hardened processor, based on a COTS workstation processor, that can be used cost effectively for most space computer applications.

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