UPDATE: June 6, 2004: Added Reference 2.
DATE: August 3, 2002
Here is the fourth in a series of OLD News articles.
It has been observed that many digital systems are not properly analyzed but are "qualified by test." Upon examination and analysis of the design, it is found that unreliable design practices are used and that proper timing margins can not be guaranteed. Use of high-skew clocks is a typical case with no guarantee of adequate hold time (tH) margin. However, the argument is made that the system passes all tests.
First, without proper analysis, one can not show that temperature coefficients of all circuit elements in the FPGA will "track." Indeed, voltage and temperature testing at the environmental limits is insufficient. A number of improperly designed systems have shown "singularities" where the system, in the lab, would fail over a small range of temperature.1
Secondly, and the point of this article, the assumption that delays will track over time is demonstrably a false assumption. Figure 1, below, comes from the Actel 1995 Data Book which contains a paper from 1992. Figure 2 below comes from the raw QML lot qualification data for the RH1280. This set of data shows, that for microcircuits from both commercial and high-reliability fabrication facilities, one can not assume that propagation delays will track over time.
Figure 1. Change in delay time from a 1000 gate
gate after 1000 hours dynamic burn-in at 125 °C and 5.75V.
Figure 2A. RH1280 Change in tPD after 1000 hour
life test. Tested at 4.5V, 125 °C. Data shown in ns.
Figure 2B. RH1280 Change in tPD after 1000 hour
life test. Tested at 4.5V, 125 °C. Data shown in per cent.
1 A5_Erickson_S.ppt, A5_Erickson_S.PDF (presentation)
A5_Erickson_P.doc A5_Erickson_P.pdf (paper)
From the 2000 MAPLD International Conference.
2 "RT54SX72S: Propagation Delay vs. Life," June 6, 2004.
In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to tech tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items. [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: firstname.lastname@example.org.]
All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.
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