DATE: May 17, 2002
Here is the second in a series of OLD News articles.
It has been noted for many years that startup current transients in FPGAs need special attention. This has been summarized in the section "Startup Transients and Requirements" of the November 2000 edition of Programmable Logic Application Notes:
In general, both Actel and Xilinx devices have to "start"; the Actel devices like the power supply to rise quickly while a fast rise time will require higher current levels in the Xilinx technology.
A recent evaluation by ESA shows transient current data as a function of dose for the XQVR300 and out of specification behavior at lower levels than previously reported.
Radiation Evaluation of Power-Up Behaviour of Xilinx FPGA XQVR300
January 21, 2002
Parameter drift, supply leakage current and time delay measurements indicate small drifts after irradiation.
The critical parameter is the current peak at power-up. After 45 krad(Si) accumulated total dose severe problems to initialise the devices were indicated. It was observed that the current peak in the power-up phase strongly increased in width and amplitude with cumulated total dose. The two tested power-up ramps indicate that a higher total dose tolerance could be achieved with a slower power-up ramp. Xilinx allow up to 50 ms power-up ramp.
The present results are in conflict with earlier total dose tests performed by Xilinx where total dose tolerance to about 100 krad(Si) have been reported. 2,4 These tests have, however, been performed on blank devices with no power cycling during irradiations.
2 Joe Fabula and Howard Bogrow, Total ionizing dose performance of SRAM-based FPGAs and supporting PROMs, MAPLD 2000, Oct. 2000.
4 Earl Fuller, Michael Caffrey, Anthony Salazar, Carl Carmichael and Joe Fabula, Radiation characterization, and SEU mitigation, of the Virtex FPGA for space based reconfigurable computing, NSREC 2000, Oct. 2000.
In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to tech tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items. [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: firstname.lastname@example.org.]
All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.
Home - NASA
Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz