Date: April 7, 2004
It is the job of the designer/analyst to engineer systems that meet mission requirements and parts specifications, which are typically derated for high-reliability systems; thus, the system margins are increased by designers "moving to the left." Similarly, the device manufacturer must engineer devices whose performances meet or exceed all of the specifications; system margins are increased by producing more robust parts as the manufacturers "move to the right." Overall positive and large margin enables reliable systems that are tolerant of the inevitable design/analysis errors, the weakest parts in a family of devices, and off-nominal conditions. It is inevitable that these conditions will occur.
Several recent documents have discussed this issue in detail for Actel SX-A and RTSX-S FPGAs:
- "The First Summary Report on the Independent Review of RTSX-S FPGA Reliability on NASA Space Flight Missions," February 11, 2004.
- OLD News #14: "Testing and Application of Modern Microelectronic Devices: Do's, Don'ts, and Failures," November 19, 2003.
- OLD News #15: "Actel SX-A and RTSX-S Programmed Antifuses," March 17, 2004.
- NASA Advisory NA-GSFC-2004-06: "Actel RTSX-S and SX-A Programmed Antifuses," March 26, 2004.
This note consists of a data set to complement the references above. In this case, the manufacturer of the FPGAs, the Actel Corporation, is experimenting with a new programming algorithm. This raw data has been supplied to the NASA Office of Logic Design for dissemination to the user community, to ensure that each program can make an informed decision with the best available data in a timely manner.
The tests were performed by Actel on two sets of 0.25 µm FPGAs (MEC): one set was programmed with the current production algorithm and the other set was programmed with a new programming algorithm. The tests subjected the devices to a "dirty burn-in." As defined in Reference 1, above, a "dirty burn-in” is a test where the electrical environment the part is subjected to is outside of the device manufacturer’s specifications.
An update to this note will be published when the qualification testing has been completed. At that time, NASA Advisory NA-GSFC-2004-06 may also be updated, dependent upon the test results.
New Programming Algorithm
See updates below for latest totals. This page is acting as a running test log.
Results with current Production Algorithm (MEC)
- 12/322 at 168 hours “dirty” burn-in (out of spec -1.1V undershoots on I/Os). All failures isolated to single antifuse failures.
- 0/225 at 500 hours “dirty” burn-in
- This represents a worst case Lot Tolerance Percent Defective (LTPD) of 7 (12 failures allowed with 254 units )
Results with new Programming Algorithm (MEC)
- 0/363 at 168 hours “dirty” burn-in (out of spec -1.1V undershoots on I/Os)
- 0/143 at 500 hours “dirty” burn-in
- This represents a worst case LTPD of 0.5 (0 failures with 328 units)
Temperature Cycling Tests
- 129 units passed 100 cycles, -65 °C = t = +150 °C, per JEDEC spec JESD 22 A104 condition C.
- No errors were detected. The devices were functionally and parametrically tested before and after the test.
- 129 units going through the Temperature Cycle (TC) testing have successfully completed the 500 TC and post TC functional and DC parametric tests.
New Algorithm currently in Qualification Testing
- Schedule to be released Mid-May
Update, April 8, 2004: Temperature cycling range corrected, was -55 -10/+0 °C = t = +125 -0/+15 °C.
Note, April 16, 2004: Test data is taken with VCCA = 2.75V, nominal.
Update, April 19, 2004: The 12 failures with the production algorithm were all isolated to single antifuse failures.
Note, April 21, 2004: Test vehicle is the A54SX72A-PQ208.
Update, April 21, 2004: New results for temperature cycling tests, 500 cycles completed.
Update, May 5, 2004:
The HTOL life testing for the 3 qualification lots and the officially designated 129 units has completed with no failures. At this time the total number of units from 5 different production shippable MEC A54SX72A wafer lots (minimum 100 parts per lot) in "dirty" HTOL Burn-in testing is as follows:
705 Units all passing after 168 Hour pullpoint testing
541 Units all passing after 500 Hour pullpoint testing
342 Units all passing after 1000 Hour pullpoint testing
Approximately 20 I/O's toggling simultaneously. VCCA = 2.75V, nominal. VCCI = 5.25V, nominal.
The Software Quality Assurance testing for the new programming algorithm integrated into the full Silicon Sculptor software package is all that remains. All Actel reliability testing requirements have been met. Target shipment for software is 5/19/2004. This will be version 4.44.0/Windows and version 3.81/DOS
Update, May 13, 2004:
- Results with New Algorithm (flight RT54SX32S-CQ208)
- 0 failures out of 100 devices at 500 hours
- Note: preliminary measurements indicated -2.0V of undershoot for this experiment
Update May 17, 2004:
- Additional data has been collected with the A54SX72A and the old programming algorithm. These devices were control units running concurrently with devices configured with the new programming algorithm.
- Old algorithm summary: 16 failures out of 623 units, 168 hours of "dirty burn-in." Failures are a damaged programmed antifuse. A54SX72A.
- New algorithm summary (dirty burn-in), A54SX72A.
- 0 failures out of 705 devices, 168 hours
- 0 failures out of 605 devices, 500 hours
- 0 failures out of 342 devices, 1000 hours
- RT54SX32S-CQ208: 0 failures out of 100 devices at 500 hours of "dirty burn-in".
- RT54SX72S devices are currently in the temperature chamber, under test.
- Test Vehicle: RT54SX72S-CQ208B(MEC)
- Test: Dynamic Programmed Burn-in (HTOL)
- Design: Actel Qualification Burn-in (QBI)
- Approximately 20 I/O's toggling simultaneously with an undershoot of approximately -2.0V (absolute maximum specification of -0.5V).
- Quantity: 102
- Temperature = 150 °C
- VCCI = 5.5V
- VCCA = 2.75V
- 184 Hours
- No Failures detected
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