NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


OLD News #12

Summary of Recent EEPROM Failures

Update: September 17, 2003, added Reference 6.

Update: September 20, 2003, added References 7 and 8.

Update: February 23, 2004, added Reference 9.  Note also that since posting this note, a number of additional users have written in concerning problems with these devices, adding to the database.

Update: July 21, 2004, added Reference 10.

Update: October 17, 2004, added Reference 11.

 

Date: July 3, 2003

This is the twelfth in a series of OLD News articles.

Summary and Conclusion

EEPROM technology-based devices are attractive components since they are both rewritable and non-volatile.   Many of the products used in civil space systems are based on the Hitachi 1 Mbit commercial die.  They are packaged by various vendors into either single chip packages or multi-chip modules. 

Bit failures, in two distinct EEPROM die, were reported on a flight instrument in the first year and a half of flight, with the initial analysis concluding that these were due to random defects.  The analysis, however, could not be supported and a wider survey of EEPROM usage was conducted by various NASA Centers and contractors.  It has been found that there have been a number failures ranging from single bit to page loss.   The number of failures relative to the small sample size causes serious concern.

Features should be incorporated such as permanent fixed memories and/or DMA that is independent of processor actions, so that either the EEPROM or other memory devices can be reloaded and/or patched if data becomes corrupted.  Failure of EEPROM devices is a credible scenario that can not be dismissed.

Note that the projects have not yet determined the failure mechanisms or root causes for any of the in-flight or ground failures.

Device Characteristics

All of the devices in this report are based on the Hitachi HCN58C1001 Mbit EEPROM die.   These devices are (commercial part numbers):

Basic characteristics of the die are:

Summary of the Failures

Genesis Failure #1

Approximately 6 months into the mission, a bit failed.  The contents should have been a '0' but readback indicated it was a '1'.

Genesis Failure #2

Approximately 13 months into the mission, another bit failed.  The contents should have been a '0' but again readback indicated it was a '1'.

Mars Exploration Rover Failure #1

December 5, 2002: Page failure was detected during breadboard test.   It was pattern sensitive and there was a bit of trouble getting the problem to repeat after the device was removed from the system.

Mars Exploration Rover Failure #2

March 1, 2003: Numerous fluctuating errors were found during pre-launch testing that were all confined to a single page of the device.  The values continued to fluctuate for over an hour after being written and were still fluctuating when testing ceased.

Mars Exploration Rover Failure #3

December 5, 2002: Three bit errors were reported in one page with only the last one verified.

Deep Impact HRI Failure #1

October 31, 2002: After programming and verification, the board was left unpowered for several days.    The failure started out as a single location but as time went on the failures seemed to be in an address region and not a single location.

References

  1. "Maxwell EEPROM Bit and Page Failure Investigation Report," Y. Chen, June 3, 2003.   e-mail for access
  2. Military Specifications for Memory Devices
  3. Austin Semiconductor EEPROM Standard Products
  4. Maxwell Technologies Microelectronics: Components - Memory
  5. 256K Paged CMOS E2PROM FM28C256 Failure
  6. "EEPROM Bit and Page Failure Investigation," Yuan Chen, Rich Kemski, Duc Nguyen, Frank Stott, Ken Erickson, Leif Scheick, Richard Bennett, and Tien Nguyen, 2003 MAPLD International Conference, Washington, D.C., September 9-11, 2003.   Abstract: chen_a.pdf;
    Presentation: p10_chen_s.ppt - Paper: "EEPROM Bit and Page Failure Investigation,"
  7. Reliability Report: HN58C1001 Series CMOS 1M EEPROM
  8. EEPROM Evaluation and Reliability Analysis, Aerospace Report No. TOR-2000(3000)-01
    June 28, 2000.  e-mail me for access.
  9. "Experiences in Qualifying a Commercial MNOS EEPROM for Space," E. E. King, R. C. Lacoe, G. Eng, and M. S. Leung The Aerospace Corporation, 2001 Non-Volatile Memory Technology Symposium.
  10. "Independent Team Review - EEPROM Bit Failures in the RAD6000", November 5, 2003.
  11. "Usage of EEPROM in Digital Designs," Saab Ericsson Space, D-G-NOT-00385-SE, 2004.

In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to technical tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items.  [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: richard.b.katz@nasa.gov.]

All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.

whats_new.htm

Best regards,

-- rk


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