May 16, 2003
OLD News #10.
Update: June 17th, 2003: pcn0304_inrush.pdf
Update: August 6, 2003: icci_inrush_sx-x_data_nasa.pdf - This adds new data on the RT54SX72S
Update: November 17, 2003: p79_elftmann_p.pdf - Paper P79 from the 2003 MAPLD International Conference.
Inrush or startup current has been an issue for as many years as FPGAs have been used in digital aerospace electronics. Information on this has been published in a number of different place, including:
OLD News #2: Startup Current Transients for FPGAs
With the relatively new RT54SXS series, some new issues have recently emerged. Those are the subject of this OLD News and a field alert from the manufacturer is included below this background section.
The first device in the RT54SXS series was the RT54SX32S and was subject to an evaluation in the radiation chamber, both for total dose and single event effect performance. One finding was that the propagation delay, tPD, was sensitive to total dose in what the manufacturer calls "Rev 1 material." The manufacturer made changes to the design of the charge pump and implemented that in the next device produced, the RT54SX72S. A radiation test showed that the tPD of the device was now not very sensitive to total dose. The results are shown in the chart below, where the 10% line used as a reference as a common standard used in worst-case analyses.
tPD for Revision 1 RT54SX32S and RT54SX72S
tPD for Revision 2 RT54SX32S
After these tests several changes were made to the next revision of the RT54SX32S, including the change to the charge pump. Tests verified that the total dose propagation deltas were now under control. This charge pump change is a contributing factor for the high startup current phenomena.
The detailed explanation of the high current is explained at the circuit level in the alert below. However, the fundamental issue is that charge remains on the circuit connected to the output of the charge pump when the device is powered off. Thus, when leakage currents are higher, as during high temperature operation, the leakage currents increase, resulting in shorter times required for draining the charge. Likewise, there is more difficulty when operating at cold temperature since leakage currents are less. The RT54SX72S, with many more connections to the charge pump, inherently has higher leakage currents. This is the explanation given by Actel for the lack of an issue in the RT54SX72S. However, we all should be aware of this issue and test and analyze all of our circuits.
There has been a lot of unreleased documentation from the manufacturer that has been circulating, including claims of start up current transients of 4 A. Actel has not observed any devices drawing 4 A. Please refer to the alert below for details.
Lastly, note that the tables in the alert below do not have rows for -55 °C. The manufacturer provided this explanation:
We have investigated ~30 devices with variations within the bounds outlined in the alert below. The recovery time at -55 °C was not collected because of the difficulty of collecting this data. The engineer had to wait a period of time and bring up the device with a low compliance on the power supply setting, as soon as the high current was observed the device was switched off again and the next sample time scheduled, this continued until no high current was observed. Once a baseline was established the experiment was then repeated, due to the fact that the turning on of the device, even with the compliance setting altered the true recovery time as power consumed by the device contributes to die self-heating increasing the leakage and altering the true recovery time at a given temperature.
This OLD News will be updated with additional data as it becomes available.
Recently a copy of "Actel Advisory Draft Rev 0.3" has been circulating throughout the industry. The information contained in that alert is incomplete and not accurate. Please disregard and dispose the aforementioned alert immediately. This alert is the notification of the RT54SX32S High ICCI Inrush current issue.
It was recently observed that for a particular (listed below) power cycling sequence of VCCI and VCCA, a high ICCI inrush current was noted when the time between power cycles was short.
This phenomenon was observed for the following power cycle sequence:
- Device powered with VCCI and VCCAON
- Power down VCCI and VCCA
- Power up device immediately (order of few seconds) with VCCI only
- I/Os are left floating during this condition.
Only the above defined mode of power cycling has shown to measure high ICCI (1.2 A maximum was observed) when powered up the second time. There are no device reliability concerns and no functional failures of the Actel device can result from this anomalous behavior.
Description Several experiments were conducted at Actel to narrow the root cause and source of this high current. Based on the findings here is an explanation of this high current. Figure 1 is a schematic representation of the I/O buffer. As shown in figure 1, the transistors circled were shown to light up during Liquid crystal testing indicating it to be the source of high current.
During normal power-up, the PMPOUT signal (comes from a circuit referred to as Charge pump) is at a low state. This will cause the PDGATE node to be pulled up to a high state by the transistor T3. The PDGATE will also turn the transistor T4 ON and pull the PDGATEB to a low state as a result turning the output transistor T2 OFF. After power-up, the PMPOUT will be at a high state and the state of the PDGATEB will depend on the state of PD, which is driven by VCCA.
The reason for the high current when only the VccI is powered up immediately after powering down both supplies is that there is some residual charge still left on the PMPOUT line. The charge on PMPOUT will turn the transistor T3 OFF. The final state of the latch formed by T5 and T6 is indeterminate. The state of PDGATE and PDGATEB will depend on which of the transistors turn ON first. There is a 50% chance that T6 will turn ON first and 50% chance that T5 will turn on first. The result of PDGATEB being pulled up to VCCI turns T2 ON. The same circuit probabilities apply to the PUGATEB signal. If PDGATEB is high and PUGATEB is low then the totem pole current (IT) will result. The combined probability of these 2 signals being in the state which causes current to flow is as follows:
0.5 x 0.5 = 0.25 or 25%
Figure 1 I/O Buffer Schematic Representation
The reason why the anomalous behavior is not seen for the blank devices is due to the fact that the PMPOUT is not turned ON for blank devices. To confirm the above theory that the charge left on the PMPOUT line was causing the high current, a FIB (Focussed Ion Beam) pad was placed on the PMPOUT for micro-probing. The device was then put in the high current condition. The PMPOUT signal was then terminated to ground, through microprobe, to dissipate the charge. The high current disappeared as soon as the PMPOUT was grounded, which proved that this was the cause of the high current.
With 25% mean and 3*sigma, the minimum number of I/Os can be estimated to be 42 and maximum of 82.
Based on several experiments conducted at Actel the following conclusions can be made regarding this high current behavior:
- The current pulse (ICCI) presented in this letter applies to customers using the RT54SX32S FPGAs under the following conditions:
- Rapid power cycling (on-off-on)
- VCCI powers-up before VCCA
- VCCI reaches ~1.2 V long before VCCA reaches ~0.7V(since the totem pole current disappears once VCCA reaches 0.7 V)
When the above conditions are satisfied, a current pulse of approximately 1.2 Amp may be realized on the VCCI power supply. Table 1 provides the observed recovery time of multiple devices.
Table 1. Observed Recovery Time
Temp °C Minimum Recover Time (s) Maximum Recovery Time (s) 0 700 1900 25 15 150 40 8 45 65 2 8
- This phenomenon is observed only on programmed units (since charge pump PMPOUT turns ON after the device is programmed)
- There are NO device reliability concerns. Electro-migration (EM) analysis shows that the devices can operate for 20 years under worst case conditions.
- No functional failures of the Actel device can result from this anomalous behavior.
- Temperature testing of devices showed the recovery times to be shorter at high temperature and longer at cold temperature. This is because transistor leakage is a function of temperature.
- RT54SX72S does not exhibit this behavior.
- This behavior is independent of the customers design
- This behavior is independent of the wafer lot.
Short Term Solution
To avoid the high current state, Actel recommends to use one of two options:
- Power up VCCA to at least 0.7 V before VCCI after the first power cycle
- Add significant delay after power down to next power up cycle to avoid the additional current. This delay will depend on the temperature at which this power cycling is done (see Table 2).
Table 2 Power-Cycling Delay Recommended to Avoid High IccI
Temp °C Time (minutes) -30 371 0 45 25 4.3 40 1.2 65 0.183
Long Term Solution
An application note is being written to address the details of this issue, and the RT54SX-S datasheet will be updated to reflect this information. Actel cannot give any specific recommendations for power-up solutions on customers boards, since each board and application may require a different solution. However, if one of the conditions outlined in short-term solutions is satisfied, this issue can be prevented.
Actel alert in .pdf format
In my new OLD (Office of Logic Design) position, I am now making some of my informal e-mail lists semi-formal. These mailings will have pointers to technical tips that can [hopefully] proactively prevent errors from getting into flight designs or make things go faster and smoother. I have included an array of people from a number of number of organizations; different NASA Centers, ESA, etc., as you all may distribute to people in your own organizations and other colleagues. Please let me know if you are on this list in error or if someone should be added to it. This list is targeted towards those that either will design or review space flight digital electronics. Feel free to suggest topics for discussion and research or to contribute news items. [Note for this web-based release: to become a recipient on this mailing list, please send e-mail to: firstname.lastname@example.org.]
All application notes are uploaded onto my www site. New additions are noted on the what's new page. I will give these mailings from time to time; too much and they will be filtered and ignored - too little and not enough information flows. So I'll try and hit a good balance.
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