NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

MAPLUG

Military & Aerospace Programmable Logic User's Group

User Notification

NASA Advisory NA-GSFC-2005-04	Problem Description and Details (partial) Reports of failures associated with the use of Electrically Erasable Programmable Read Only Memory (EEPROM) technology-based devices used by the aerospace industry have recently become widespread. Documented failures center around systems based on the Hitachi HCN58C1001 1-Mbit commercial die. The Hitachi die is packaged by various vendors into either single chip packages or multi-chip modules. This advisory is applicable for the use of Hitachi 1-Mbit die based components in both custom in-house designs as well as integrated into commercially available products as is the case with flight computer boards available from several vendors. Note: Hitachi no longer makes this die and the organization which previously made the die is now part of a different company.
Destructive Physical Analyses (DPAs) on Field Programmable Gate Arrays (FPGAs) and Non- Volatile Memory Devices, Failure Reports, and Lessons Learned NASA Advisory NA-GSFC-2006-01 January 12, 2006	Summary In both FPGA and EEPROM device applications, the realization of past parts issues was delayed, since the failure rate was low. Failures in non-flight parts are not always treated with the same rigor as failures in flight qualified devices. Additionally, proprietary and stove-piped information barriers, along with a cultural resistance to discussing failures, prevent the user community from pooling their data collectively, observing trends, and “connecting the dots.” Together, this had led to delays in manufacturers improving their parts, processes, and software. NASA GSFC kindly requests other NASA and non-NASA programs and projects to share with the Advisory Technical Point of Contact (see block 13) all DPA and Failure Reports on FPGAs and non-volatile memory devices, from both flight and engineering model usage along with lessons learned that can benefit the community. Note that prior to dissemination on the NASA Office of Logic Design web site, appropriate care (i.e. deleting items such as contractor names) will be taken.
Test Problem with EEPROMs EA-2005-EEE-12-A October 31, 2005	Summary 4 Mbit EEPROMs delivered and not tested properly. The programmability of every memory cell in the 4 Mbit EEPROMs have not been verified. Failures experienced on two different 4 Mbit EEPROM devices have been found during memory writing using page write mode. The failure appears as half-page that becomes un-programmable after few write cycles. As the test progressed more bits became stuck at 0 in the second half of the page.
Product Discontinuation Notice: MEC RT54SX-S 0.25 µm FPGAs September 6, 2005 PDN Number: 0504	Summary Numerous tests conducted by Actel Corporation (Actel) and third parties have confirmed that the RTSX-SU devices manufactured by United Microelectronics Corporation (UMC) have lower FIT rates than the RTSX-S devices manufactured by Matsushita Electric Industrial Co., Ltd. (MEC). Actel has offered to accept the return of RTSX-S devices manufactured by MEC in exchange for RTSX-SU devices manufactured by UMC, and Actel’s customers have overwhelmingly decided to switch from RTSX-S devices manufactured by MEC to RTSX-SU devices manufactured by UMC. For both of the reasons summarized above, Actel decided to stop manufacturing RTSX-S devices at MEC.
NASA Advisory: Actel SX-A, RTSX-S, and RTSX-SU FPGAs in Mission and Safety-Critical Systems. November 29, 2004 NA-GSFC-2005-01	Actions Recommended: Actel MEC SX-A FPGAs should not be used in safety-critical applications. Actel MEC RTSX-S FPGAs should not be used in manned, safety-critical applications. These two recommendations apply to both the “old” and “new” programming algorithms. Some faults present in the flight hardware may be undetectable. Other premature failures may manifest themselves after the conclusion of the test program. Current and prospective users of Actel UMC A54SX-A and the new Actel UMC RTSX-SU FPGAs are urged to follow the NASA Office of Logic Design UMC device testing progress (See www.klabs.org for latest results). Actel internal testing has detected no programmed antifuse failures on these two UMC device types. It is recommended that projects employ the following three techniques to decrease the risks associated with the usage of Actel MEC SX-A and Actel MEC RTSX-S FPGAs (Note: also recommended for Actel UMC FPGAs): Ensure that test procedures have maximized fault coverage and all circuit nodes are heavily exercised. Maximize the number of operating pre-launch hours, in particular high temperature environmental testing. Ensure that all specifications, manufacturer’s guidance and good engineering practices are always followed with conservative design practices employed. In particular, logic structures that use the routed array clocks or local signals must employ skew-tolerant clocking techniques.
Actel PCN 0408-RTSX-SU December 22, 2004	Synopsis This notice is to inform you that following the qualification of the RTSX-SU product family, Actel has made a single mask change to improve manufacturing yields. Qualification was conducted and has validated that the change still meets the applicable released technical specifications. Therefore, the RTSX-SU product family remains unchanged in form, fit, functionality, and reliability. The affected devices are RTSX32SU and RTSX72SU with all speed and package combinations.
NASA Advisory: Testing of Actel SX-A and RTSX-S Programming Algorithms June 22, 2004 NA-GSFC-2004-08	Recommendations Actel has released and recommends use of a new programming algorithm for the SX-A and RTSX-S devices built in the 0.25 micron MEC/Tonami process. Users must note that the qualification program was conducted at high temperatures only and that comprehensive temperature data is not yet available. NASA will produce a comprehensive data set, including both cold (-55 degrees C.) and hot (+125 degrees C.) temperatures, under the sponsorship of the NASA Engineering and Safety Center (NESC). Test devices will consist of 300 RTSX-S 0.25 µm MEC devices and 300 RTSX-SU 0.25 µm UMC devices. For further information, contact Rich Katz or your resident FPGA expert. Users retain the option of using the old programming algorithm by not upgrading their software and must note that there are a significant number of programmed antifuse failures that are under investigation (Reference: NASA Advisory NA-GSFC-2004-06). All relevant personnel must also review NASA Advisory NA-GSFC-2004-06, and the documents referenced, to ensure that all specifications, manufacturer’s guidance, and good engineering practices are always followed and conservative design practices employed.
Designer Software Error for QCLK Macros (A54SX72A, RT54SX72S) March 25, 2004 qclk_3_2004.htm	Summary This advisory is to inform the users of the Designer software version 5.1 and prior versions that when creating designs containing both QCLK Buf and QCLK Int macros for the A54SX72A and RT54SX72S devices, functional time zero failures may result. These failures are immediate; any designs that have passed initial functional test do not have these problems.
NASA Advisory: Actel RTSX-S and SX-A Programmed Antifuses. NA-GSFC-2004-06 March 26, 2004 na-gsfc-2004-06.pdf	Actions Recommended: All relevant personnel should ensure that all specifications, manufacturer’s guidance, and good engineering practices are always followed and conservative design practices should be employed; failure to follow such an approach appears to correlate with device failure.
*TRST and the IEEE JTAG 1149.1 Interface.** NA-GSFC-2004-04 na-gsfc-2004-04.pdf	Problem Description and Details: During project reviews, the NASA Office of Logic Design has found instances of flight hardware that had microprocessors and FPGAs with improper configuration of the TRST* pin and the IEEE JTAG 1149.1 Interface. Therefore, it is essential that the designers, analysts, and reviewers read the attached technical article, which emphasizes the design fundamentals of the proper termination of the TRST* pin and the IEEE JTAG 1149.1 Interface.
Out of Compliance Solder and Upsets in XC2V FPGAs	Product Advisory Xilinx recently released an advisory about some FPGAs in flip-chip packages were manufactured using solder that may cause upset of configuration memory bits. It was determined that out of compliance "low-alpha" solder was used.
OLD News #10: RT54SX32S High I_CCI Inrush Current Additional Information: pcn0304_inrush.pdf	Summary It was recently observed that for a particular (listed below) power cycling sequence of V_CCI and V_CCA, a high I_CCI inrush current was noted when the time between power cycles was short.
Xilinx: Product Change Notification PCN2001-05 Xilinx: Customer Update XCU2000-02: Design Process Marginality on Virtex 32x1 Distributed SelectRAM	Abstract Subject: The Virtex™ family contains a design process related marginality that may affect functionality of the distributed (LUT-based) SelectRAM when configured in a 32x1 mode. It is recommended that customers do not use these devices in this mode. This marginality issue occurs when a customer write enables data into the LUT. The write strobe signal that loads the data into the memory cells is not wide enough to accommodate the full range of process variation across the die. The device then fails since some of the data was not written to the memory address location. The failure is seen as a random LUT failure typically at a single location within the array.
SMD_Error_DESC_5962_95521.html	Typographical error contained in the Standard Microcircuit Drawing (SMD) number 5962-95521 (Actel generic part number A14100A) is fixed.
RH1020_Special_Pins_Advisory.htm SDIreport.pdf	Issue on the use of the SDI and DCLK pins in some date codes of the RH1020 and RT1020s. SDIreport.pdf added 1/17/2002.
StartupNote.pdf	Startup Considerations for Certain Programmable Devices and Oscillators.
NASA_Advisory_046_ActelStartup.pdf	NASA Advisory on startup of current Actel Field Programmable Gate Arrays

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Last Revised: February 03, 2010
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