CLOCK SKEW: Failure to properly manage clock skew is a major source of failures in FPGA designs. There have been a number of instances where ‘proven’ designs have failed when the flight devices were installed into ‘working systems’ or intermittents would be eliminated by re-routing a device. The causes of these failures was twofold: improper understanding of clock skew inside FPGAs and models which did not accurately reflect delays within the device.
The Actel anti-fuse based FPGAs provide high-speed, low-skew global and quadrant clocks. There is one global clock for the 1020 devices, 2 global clocks for the 1280’s, 3 global clocks for the 1460/14100’s (two routed, 1 dedicated), and up to 6 clocks (two global, 4 quadrant) in some models of the A3200DX family. For the Act 1 A1020x devices, the user can instruct the placement and routing software how much effort to expend on clock balancing, trading off clock skew for system performance. The other series devices have improved clock networks where this is not necessary. So, by appropriate ‘balancing’ in the Act 1 family and normal usage of the global clocks in the other devices, clock skew is normally not a problem. Adequate timing margins can easily be calculated using TIMER.
When regular signals are used as clocks, care must be taken to ensure that setup and hold times are guaranteed to be met. Routing clock signals inside of an FPGA is not the same as routing a clock on a printed circuit board (PCB). Signal propagation delay is often negligible on a PCB and is frequently neglected as a major source of clock skew. However, for example, proper clocking is sometimes difficult when using CD40xxB logic where clock signals may have long transition times and flip-flops can have threshold varying from 30% to 70% of VDD. This can result in the parallel clocking problem where hold times may not be met since the data to the flip-flop may change prior to the clock signal reaching the logic thresholds. Since signals routed in an FPGA must propagate through a number of segments and antifuses, the arrival of the clock at various points on a network will not occur at the same time. This results in clock skew and an equivalent problem to the CD40xxB parallel clocking problem.
Certain structures are extremely sensitive to this. For example, shift registers, which have little or no logic between stages, are very prone to failure. A change in either supply voltage or temperature can cause problems to appear and disappear. In general, any structure that employs parallel clocking needs to be carefully looked at. Also, soft macros appear to have a common clock input. They don’t. It is a soft macro and the clock will propagate down a clock tree with skew between the leaves if not on a low-skew clock bus. So, easy to use macros like the TA161 counter or macros generated by ACTGen which are guaranteed to be correct by construction can fail if improperly clocked although they appear fine on the schematic.
Compounding this problem are the models used to simulate the designs. At two different contractors these issues were explored in depth to analyze their failing systems with both groups performing full simulations. However, they used a logic simulator to perform their timing analysis and either didn’t use or improperly used TIMER. In both cases, however, the logic simulator did not model the clock skew between flip-flops, assumed all clocks arrived at the same time, and ‘passed’ the circuits.
There are a number of different solutions to these types of problems and some will be briefly discussed here. First, if the design can be made synchronous, use the global clocks. The hard macros supplied by Actel minimize the pain caused by the architectural limitation of a small number of low-skew clocks. These macros include flip-flops with enables and flip-flops with multiplexors on the inputs. Another approach is to utilize a structure where flip-flops that communicate pass data between opposite edges of the clock. This moves a clock skew problem into a clock width consideration and possibly a device utilization issue. A more compact solution but with more complexity is to use a two-phase non-overlapping clock structure with one-module latches. Another technique is, where possible, to eliminate the use of synchronous counters and use ripple counters or a hybrid counter where the first stage is synchronous which feeds the remaining stages that operate in a ripple mode.
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Last Revised: January 09, 2002
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