| Abstract: A sampling of waveforms from the LOLA flight model. Outputs of 54ACS132 and RTAX2000S (high and low slew) included. |
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You need to register and get a password to obtain the models. |
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July 18, 2004. |
Abstract During the development of flight hardware, it was suggested that outputs in a particular design be switched to low slew since high slew drivers were not needed. Since the first unit was already built with high slew drivers, the second unit, on an identical circuit board, was built with low slew drivers. Data was obtained (see below) and the project engineers decided to retrofit the first unit with low slew drivers. |
Dr. Rod Barto |
Synopsis A "before and after" look at printed circuit board artwork with respect to bypass capacitor connections. |
| Introduction Many modern CMOS digital microcircuits have very strong drivers; the device characteristics have changed over the years. Another change is the widespread use of HDL synthesis for logic generation and simulators for logic simulation. These simulators do not replace the need to perform proper electrical engineering of spaceborne digital electronics, in particular signal and power integrity. |
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LUNA-C DD3 16M (4Mx4) DRAM with On-Chip ECC |
Summary Signal integrity is important for all devices, of course and it is noted that signal integrity requirements are usually treated as an aside, even by the manufacturers, as well as the user. However, many DRAM and SDRAM manufacturers make signal integrity requirements very prominent and explicit -- this is not done to make their parts harder to use! IBM has carefully specified requirements for their 16 Mbit DRAM and the key figures and text is presented below as one specific example. As always, consult specific data sheets and application notes for each particular design. |
RT54SX-S tR/tF Experiment June 14, 2002 |
Issue Actel understands that customers may have difficulty meeting the 10ns tR and tF specification of the RT54SX-S devices for certain applications. As reported by customers in their application of RT54SX-S programmed parts the maximum fall transition time specification could exceed the limits of the Actel data book for these parts. This may occur during a bus tri-state operation where there is no active pull up or pull down of the bus voltage and only a passive resistor of large value (~100 kohm) to ground to discharge the bus. In this type of application, the only concern will be when the customer design has implemented an input or bi-directional user I/O function connected to the bus. The tri-state buffer implementation in an RT54SX-S device disables the input buffer and will not be a concern. With a corresponding large bus capacitance (~2700pF) the resulting fall times for input pins from the tri-stated bus operation on these or any similar Actel parts would be on the order of 500 µs, exceeding the specified 10ns maximum transition time. There may be concerns for functionality issues during the tri-state conditions as well as long-term reliability concerns. This report summarizes the findings of fall time experiments completed to determine any potential reliability issues with slow fall times. (June 20, 2002). |
actel_ibis_appnote.pdf |
IBIS Models: Background and Usage Introduction For better understanding of the signal integrity on printed circuit boards (PCBs), hardware designers often need to simulate the design with I/O characteristic models. The designer must carefully consider signal integrity issues such as deformation of electronic signals as they travel on the PCB, cross talk, ground-bounce and simultaneously switching outputs (SSO). Input/Output Buffer Information Specification (IBIS) models have been developed to address the above issues by providing I/O parameters in analog terms. This Technical Brief explains how to use IBIS models. In addition, this document discusses information contained in an IBIS model, explains what can be extracted from the model and provides examples of Actel IBIS models. [3/29/02] |
| XQR4036XL Ringing.jpg | An XQR4036XL output not properly terminated. |
| QL3025_Fall.gif QL3025_Rise.gif |
Sample Output Characteristics of the QL3025 - Sub-nanosecond Transition Times (.gif 5 kbytes each). |
| QL3025_SN3_Power.pdf QL3025_SN4_Power.pdf |
Test and Power Measurement of a Quicklogic QL3025 (no speed grade) 8-bit Ripple Counter. Obtained 500 MHz performance under room temp, 3.3 volt conditions, after a 35 kRad(Si) exposure. Power is low, even at 500 MHz. (.pdf 4 kbytes) |
| RT54SX16_Fall.gif RT54SX16_Rise.gif |
Sample Output Characteristics of the RT54SX16 - Sub-nanosecond Transition Times (.gif 5 kbytes each). |
| act3_125mhz.pdf | "Act 3 Technology at 125 MHz": Abstract: Simulations were run on a simple circuit to determine the feasibility of running Actel Act 3 devices at 125 MHz (8 nSec cycle time) with two levels of logic between flip-flops and high-slew output buffers were used. The simulations determined chip-to-chip timing as well as internal timing and were run over a variety of models, speed grades, and environmental conditions. (.pdf 15 kbytes). |
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Summary Ground bounce, potentially large enough to cause an error in sensing logic level, was observed within an Actel 54SX32A. The magnitude of bounce was a function of output driver slew rate - faster outputs increased the effect. I/O power supply voltage also affected bounce with more observed in the 5V than the 3V parts. Temperature dependence of ground bounce was more complex. Bounce appeared independent of temperature for low slew outputs and increased when the part was cold for PCI type outputs. However, the data indicated that for the high slew outputs bounce decreased when cold. While simultaneously switched output (SSO) induced ground bounce was clearly observed, application functionality in many cases should not be compromised. Most designs have only a small number of potentially sensitive signals. Pin placement and driver slew selection can dramatically reduce bounce for those signals. An engineering peer review of preliminary pin assignments may be helpful in identifying these issues and developing solutions. In case of a problem discovered after pin assignments are frozen, changes within the FPGA such as adding internal delays to stagger outputs can lessen bounce. External filter components can also be used to reduce the impact of bounce. SSO induced ground bounce does occur but many design techniques can be applied to overcome this problem. |
Ground Bounce Basics and Best Practices Phil King, Agilent Technologies |
Introduction Most electronic circuit designers are now familiar with ground bounce problems internal to integrated circuits and the ground bounce that can occur between an IC and the PC board. However, many PC board designers and board test developers are unfamiliar with ground bounce problems related to test. Ground bounce, whether at the IC, PC board, or system level is a transient voltage difference between the ground reference points in two parts of a circuit. In all cases the cause is a transient current (generally due to switching) flowing through the ground path impedance between the two portions of the circuit. As with the familiar ground bounce internal to an IC, ground bounce during board test can result in unexpected, and sometimes intermittent, behavior of the circuit being tested. This article begins with a description of the physical properties that result in ground bounce during board test, and some real-world examples. Following is a discussion of common circuit design, fixture construction, test system, and test technique related features that often combine to cause ground bounce problems during board test. There is a discussion of best practices for the board designer and the test engineer to minimize the likelihood of ground bounce induced test problems. A short description of boundary scan testing and ground bounce relationships completes the discussion. The author first encountered board test ground bounce in the early 1990’s when advanced CMOS logic parts became prevalent. These first experiences mostly involved library tests on large ASIC devices, though the phenomenon could even be found in the tests of smaller SSI parts. Today, the most commonly encountered board test ground bounce problems involve boundary scan tests. With boundary scan tests becoming increasingly common, it is important to be familiar with the causes of ground bounce and techniques used to control it. |
| High-Speed Digital Design Howard W. Johnson |
pp. 67-74
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| Introduction Many modern CMOS digital microcircuits have very strong drivers; the device characteristics have changed over the years. Another change is the widespread use of HDL synthesis for logic generation and simulators for logic simulation. These simulators do not replace the need to perform proper electrical engineering of spaceborne digital electronics, in particular signal and power integrity. |
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| I/O Characteristics of the 'XL FPGAs | Summary Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application note describes I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. Such parameters are, however, not production-tested and are, therefore, not guaranteed. |
| System Resources : Signal Integrity | Signal Integrity Central Building a working system today requires knowledge of a great deal more than just boolean logic and HDL code. The documents and links in this area are designed to give you everything you need to achieve reliable PCB designs on the first try. |
| Basics of Signal Integrity | Signal Integrity (SI) engineering has become a necessary requirement for
today's high-speed logic signals. Having control of cross-talk, ground bounce, ringing,
noise margins, impedance matching, and decoupling is now critical to a successful design. All of these problems relate to a similar issue: Signal Integrity. SI describes the environment in which the signals must exist. It covers the various techniques and design issues that ensure signals are undistorted and do not cause problems to themselves, to other components in the system, or to other systems nearby. |
| Signal Integrity Glossary | Glossary of Signal Integrity and High-Speed Signaling terms |
| Power Supply and Bypassing | With a noisy or under-rated power supply, a circuit board is an expensive
piece of garbage. xapp158.pdf is your first step in addressing FPGA power
needs. Includes other links. |
| Simulation Tools | Analog simulation is a necessary part of PCB and system design. Xilinx has
chosen to support simulation of our products through IBIS I/O models. Here's where you can
find the models and simulators to use them in. Includes other links. |
| PCB Design Considerations | There are a lot of things to get right when designing a state-of-the-art Printed Circuit Board. Take a look at the links to make sure you don't leave anything out. |
| Multi-Gigahertz Signaling FAQ | Multi-Gigahertz Signaling FAQ |
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Peter Alfke, 1997 |
Summary (excerpts) The “Absolute Maximum Ratings” table in the Xilinx Data Book restricts the signal-pin voltage to a maximum 500 mV excursion above VCC and below ground. The reason for this tight specification is to prevent uncontrolled current in the input-clamping ESD-protection diodes. Such tight specifications are common in the industry; some manufacturers limit the excursion to 300 mV. ... ... Here is the new Xilinx specification: “Maximum DC overshoot or undershoot above VCC or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to VCC + 2.0 V, provided this over- or undershoot lasts less than 20 ns”. |
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| Howard Johnson's www site. | |
| Introduction and Excerpt Signal Integrity is a field of study half-way between digital design and analog circuit theory. It’s about ringing, crosstalk, ground bounce, and power supply noise. It’s all about how to build really fast digital hardware that really works. It’s about practical, real-world solutions to high-speed design problems. Ground bounce and power supply noise will boil over. Higher-powered drivers, switching at unbelievable rates, in massive parallel bus structures, are a sure formula for a power system meltdown. Sure, throwing on more pwr/gnd pins and more bypass capacitors helps, but where's the limit? These things aren't free. You will want guaranteed glitch-free operation at a minimum cost. |
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Overview HSDD Online Newsletters, intended for serious digital circuit designers, PCB layout designers, ASIC engineers, and EMC professionals, these newsletters are filled with detailed, technical analyses of specific digital design solutions. Previously published articles in EDN and other sources. Pieces of interest to a wide audience on the topic of signal integrity. Includes pithy analyses of industry trends, good design tips and techniques, and occasional diatribes against bad design practices. |
| Overview A variety of very detailed notes on how to design with this high performance processor. |
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