NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


FPGA Application Notes

Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances

March 31, 2004

Executive Summary
  • Cosmic ray soft error rate was measured for five different architectures of FPGAs, from three different vendors, using three different programming technologies.
  • Test methodology was compliant with JESD-89.
  • SRAM-based FPGAs are liable to configuration SEU and SEFI when exposed to high-energy neutrons.
  • Antifuse-based and Flash-based FPGAs did not exhibit any configuration SEU or SEFI when exposed to high-energy neutrons.
  • Test results allowed the calculation of the ratio of SEFIs to SEUs.

TRST* and the IEEE JTAG 1149.1 Interface.


Problem Description and Details:
During project reviews, the NASA Office of Logic Design has found instances of flight hardware that had microprocessors and FPGAs with improper configuration of the TRST* pin and the IEEE JTAG 1149.1 Interface. Therefore, it is essential that the designers, analysts, and reviewers read the attached technical article, which emphasizes the design fundamentals of the proper termination of the TRST* pin and the IEEE JTAG 1149.1 Interface.

RH1280 Lifetest Delta Data


Suitability of Reprogrammable FPGAs in Space Applications: Feasibility Report

FPGA-002-01, Version 0.4
September 2002

Prepared by Sandi Habinc, compilation from various sources



The dominating reprogrammable Field Programmable Gate Array (FPGA) devices currently on the space market are from Xilinx Inc. San Jose, California, USA. The devices have a relatively good total dose resistance, but the on-chip configuration memory is soft with respect to Single Event Upsets (SEUs).

Xilinx has in several publications stated that they have developed mitigation techniques that would cancel out the effects of Single Event Upsets in their FPGAs. During the last couple of years these techniques have been updated and improved. The techniques are received with scepticism in the European space market and there has been a need for a thorough analysis of the techniques to assess their feasibility. The scope of this report is to compile and review all publications available concerning the use of Xilinx FPGAs in harsh environments.

Although Xilinx has two families of FPGAs that are targeted towards the space segment, the  XQR4000XL and the XQVR-Virtex series, this report will concentrate on the newer Virtex technology. The older XQR4000XL technology will be discussed to a lesser extent.

Clock Skew and Short Paths Timing

March 2003

Note: comments sent in, this is being updated.  -- rk

Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design principle that inputs to registers timing must be guaranteed to satisfy register setup and hold time requirements. Both data propagation delay and clock skew are important in guaranteeing these parameters. Clocking sequentially-adjacent registers on the same edge of a high-skew clock can cause timing violations or functional failure in designs.  The problem of short data paths in the presence of clock skew is very similar to hold-time violations in flip-flops. The problem arises when the data propagation delay between two adjacent flip-flops is less than the clock skew.

Silicon Sculptor Software version 3.66 DOS and version 4.29 Windows and all RTSX-72S


This is to inform Actel customers that Silicon Sculptor Software version 3.66 DOS and version 4.29 Windows and all RTSX-72S devices programmed with this software version are being recalled.


Application Note on Grounding the MODE Pin in Actel Field Programmable Gate Arrays.

February 3, 2003

GENERAL INFORMATION: This is a NASA Advisory issued by the Goddard Space Flight Center (GSFC) in accordance with the requirements of NASA Procedures and Guidelines 8735.1.

11. Problem Description and Details (excerpt): On the GOES SXI project, there was an unterminated MODE pin on one of the Actel RH1280 Field Programmable Gate Arrays (FPGAs). Although there have not been any recorded anomalies on the GOES SXI project, the FPGA long-term reliability may be impacted without the MODE pin grounded due to various possible failure scenarios. In addition, there was a similar previous occurrence on EOS AQUA, where the MODE pin was unterminated which resulted in the replacement of all the Actel FPGAs on the spacecraft.

Qualification by Test: An Example with Clock Skew



Showing design margins by test demonstrated on the ground can not be used to predict reliability on orbit for this class of circuit.  For other classes of circuits, such as the change of propagation delay between two clock edges of a crystal clock oscillator, margin testing can have some value.

Showing design margin by logic simulation can not be used to predict reliability on orbit for this class of circuit.  Most logic simulators switch models between runs -- min, typ, and max -- and are incapable of performing min-max analysis.  The simulation algorithms assume that the variable parameters track.  As seen in Figures 4 and 5, for example, showing the effects of life and antifuse resistance, this is not the case.  Real radiation environments are also a concern.  The "tracking" assumption is simply wrong and is no more than "engineering by arm waving."

(June 8, 2002)

Lessons Learned from FPGA Developments

FPGA-001-01, Version 0.0
April 2002
Prepared by Sandi Habinc


This document is a compilation of problems encountered and lessons learned from the usage of
Field Programmable Gate Array (FPGA) devices in European Space Agency (ESA) and National Aeronautics and Space Administration (NASA) satellite missions. The objective has been to list the most common problems which can be avoided by careful design and it is therefore not an exhaustive compilation of experienced problems.

This document can also been seen as a set of guidelines to FPGA design for space flight applications. It provides a development method which outlines a development flow that is commonly considered as sufficient for FPGA design. The document also provides down to earth design methods and hints that should be considered by any FPGA designer. Emphasis has also been placed on development tool related problems, especially focusing on Single Event Upset (SEU) hardships in once-only-programmable FPGA devices. Discussions about re-programmable FPGA device will be covered only briefly since outside the scope of this document and will become the focus of a separate future technical report. (April 16, 2002)



Updated note available 3/02.  Note that experiments have shown that not all devices will remain in tri-state during the power-on transient and conservative design practices should be used. (March 29, 2002).

Power-Up Device Behavior of Actel FPGAs (April 3, 2000).

ASICs... the website

ASICs... the website

This website is about ASICs or Application-Specific Integrated Circuits, which are a type of silicon integrated circuit.  A lot of material including an e-book.  External link.  (3/17/2002).

Input Transition Time Inputs to most CMOS inputs have rise and fall time limitations for reliable operation. Although most if not all programmable logic devices have at least some hysteresis on their inputs, the transition time requirements vary considerably. (1/17/2002)
RH1020 Special Pins Advisory
Advisory on the use of special pins for certain date code RH1020's and RT1020s.
SDIreport.pdf added 1/17/2002.
Sample A1020A IOH/VOH and IOL/VOL data.  (11/1/2001)
bufd.pdf "Using the BUFD and INVD Delay Macros": These macros permit interfacing clock networks to all architectural elements and will not be removed by the back end optimization tools.  (10/27/01)
act3_turn_on.htm Some sample Act 3 output transients upon the application of power.  (10/22/01)
RH1020_1280_mode_pin.pdf Termination of the VPP and Mode Pin for RH1020 and RH1280 Devices in a Radiation Environment (10/10/01)
MODE_Pin.htm GROUND THE MODE PIN.  NOW!!!!!!!!!!!!!!!!!!!!!!!!!!! (10/9/01)
Timing_Derating.htm Timing derating factors for FPGAs.  Please let me know if you can add to the database or if there are specific devices that you want added.   We'll also be including measured data as it becomes available.  (10/9/01)
Xilinx: Product Change Notification PCN2001-05

Xilinx: Customer Update XCU2000-02: Design Process Marginality on Virtex 32x1 Distributed SelectRAM


Subject: The Virtex™ family contains a design process related marginality that may affect functionality of the distributed (LUT-based) SelectRAM when configured in a 32x1 mode.

It is recommended that customers do not use these devices in this mode.

This marginality issue occurs when a customer write enables data into the LUT. The write strobe signal that loads the data into the memory cells is not wide enough to accommodate the full range of process variation across the die. The device then fails since some of the data was not written to the memory address location. The failure is seen as a random LUT failure typically at a single location within the array.

Minimizing HDL Design Errors

Ben Cohen
VhdlCohen Publishing



This paper discusses processes, methodologies, and classes of tools necessary to minimize ASIC and FPGA design errors.

(added July 5, 2001)


Variables for Designer Software - Placement and Routing (December 8, 2000).


Power Supply and I/O Notes for Actel SX and SX-A FPGAs

Note: This application note is preliminary but there is critical information for design engineers, justifying its early posting.  rk

ISD March 2000 "Moving Data Across Asynchronous Clock Boundaries"
Reduce data balidity and timing problems without reducing data rates through careful design at the interfaces.
Note: This is a link to a copyrighted application note on Integrated Systems Design's www site.  If the link becomes invalid, please contact me at: - (8/16/2000).
ESA_DesignReq.pdf ASIC Design and Manufacturing Requirements - ESA (March, 2000).
sn001_clean.pdf Photograph of our S/N 001 Programmable Flight Experiment with the following technologies: M2M PAL, M2M FPGA, M2M Programmable Substrate, quick-turn ASIC, RH1020. (.pdf 206 kbytes)
mptb_photos.pdf Photograph of our MPTB FPGA Flight Experiment (joint with Aerospace Corp. We're testing A1460As and A1280As with various shields for total dose, SEU, and antifuse rupture. (.pdf 231 kbytes)
Actel and the Antifuse White paper by Actel Corporation discussing antifuse technologies and FPGA architecture.  Both ONO and Metal-to-Metal (M2M) antifuses are discussed.  1996.
KGD, MCM, Prog. Logic and Prog. Substrates Fast Cycle Programmable High Density Electronics: Known Good Die, Multi-Chip Modules, Programmable Logic and Substrates.   
IP_FPGAs Intellectual Property for FPGAs
MetastableStates.htm A discussion of metastable states, sample calculations w/ a MTBF calculator, and a reference list.
papers.htm and presentations.htm Please see the collection of papers and presentations for more application notes and device test results.
PGA2QFPBug.htm Designer bug when converting an A14100A PGA257 to a CQFP256.    Actel provided this work-a-round and says it will be fixed in the next version.
RadShielding1.htm Some Notes on Radiation Shielding Effectiveness (.htm)
rad_summary_sirt.htm "ACTEL Radiation Summary for SIRTF/IRAC," Brief Summary of Actel Radiation Performance for the SIRTF project with an emphasis on the use of Act 3 technology.
commercial_radhard.pdf "Commercial to Radiation-Hardened Design Migration,"
This application note describes design practices that make it easy to verify timing when using commercial devices as prototypes for radiation-hardened devices.  Also given are examples of poor design practices to avoid along with improved circuit structures. (.pdf 57 kbytes)
AsynchronousLoops.htm Procedure for having Designer software detect asynchronous feedback loops in timing analysis.
HoldTimeCalculation.PDF Note on clock skew not in calculations for Designer software, 3.0 and later. (.pdf 28 kbytes).
VL_74_R@1998_Upgrade.htm "Updating from WVOffice 7.31 and Designer 3.1.1u1 to WVOffice 7.4 and Designer R2-98 on a PC"
Parametric Data.htm
IV Curves Lan109.PDF
Representative parametric test data for A14100A/MEC-UCL055 taken from the radiation lot acceptance test at 4 krads (Si) per day, stopped at 11 krads (Si).  Parametric test data, ICC start-up current transients, output I-V curves, and output transition time scope shots over radiation. Data shown for S/N LAN109; other devices similar.
JTAG_SX_WhitePaper.PDF "Use of SX Series Devices and IEEE 1149.1 JTAG Circuitry."  This white paper reviews basic 1149.1 principles, radiation results on SX Series devices, and finishes with mitigation techniques and design considerations. (.pdf 629 kbytes)
Converting Objectstore Databases

Converting Designer 3.0 and 3.1 Objectstore databases to the new format.

Programming with Old Actel Databases

Which versions of Actel software can program the .def and .fus file formats and how do I convert files to the .afm file format for new versions of the software?

Actel Commercial Equivalents

What are the commercial equivalents to the Actel RT/RH parts?

Actel Database Compatibility App note on Actel database compatibility across platforms
Voh-Ioh Curves for RT1280A, U1H486, LAN1001,4 D/C 9843.
Vol-Iol Curves for RT1280A, U1H486, LAN1001,4 D/C 9843.
Multiplication in FPGAs An overview of multiplication and their implementation in FPGAs.
BoardLevelConsiderationsForActelFPGAs.pdf Board Level Considerations for Actel FPGAs
PowerOnReset.pdf A Power-On Reset (POR) Circuit for Actel Devices - This application note includes a description of some of the characteristics of Actel FPGAs during the turn-on transient.
StartupNote.pdf Consideration of component characteristics during the startup transient.
MAPLUG FAQ - Actel Clock Tree Note on using buffers to construct clock trees in FPGAs
Changes in delays of RH1280 over a life test.
Details with plots of intermediate points.  (June 15, 2000).
RH1280_PowerUp.PDF RH1280/A1280A Power-up Characterization Report
SafeStateMachines_Synplify_1.pdf "Designing Safe VHDL State Machines with Synplify".   Discussion of Synplicity mechanism for handling the VHDL problem of trap states.   Posted 8/15/99 (Version 5.1.5a current).
DUT Designs

TD_4Strings_A14100A added January 24, 2001.
Act2_4Strings - CPGA176/A1280A - added January 29, 2001.
TD1280 for Act 2.  Added February 14, 2001.
QYH580 DUT Pattern.  Added March 13, 2001.
TD1020_FULL.  Added October 2, 2001.
TDSX72CQFP256_4Strings_Small.  Added October 16, 2001.
TDSX72CQFP256_2Strings  Added November 21, 2001

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Last Revised: February 03, 2010
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