NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


Out of Compliance Solder and Upsets in XC2V FPGAs

Xilinx recently released an advisory about some FPGAs in flip-chip packages were manufactured using solder that may cause upset of configuration memory bits.  It was determined that out of compliance "low-alpha" solder was used.

Device Estimated Bit Flip MTBF (Days)

   2VP2

246     

   2VP4

132     

   2VP7

100     

   2VP30

37     

   2VP40

25     

   2VP50

24     

   2VP70

19     

   2VP100

14     

   2V6000

26     

 


Customer Advisory:
Flip-Chip Package Substrate Solder Issue

advisory2003-10.pdfXL

Introduction
The purpose of this advisory is to communicate that some Xilinx FPGAs in flip-chip packaging were manufactured using solder material that might cause random upset of device configuration bits.


Flip-Chip Package Substrate Solder Issue

wp208.pdfXL

Introduction
Alpha particle emission in close proximity to the device circuitry is minimized by following Xilinx low alpha solder requirements on package substrate pads. One flip-chip packaging vendor’s failure to comply with these requirements has resulted in contamination by high alpha solder causing possible soft errors due to flipped device configuration bits. This white paper provides an overview on soldering material, describes the specific soldering problem, and offers some solutions.

Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal