NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

RT54SX72SU  Heavy Ion Test

UMC Die, 0.25 µm

BNL, April, 2004

This page is the report for the single event upset part of the test..  The  portions of this test concerning destructive effects  (e.g., latchup and rupture) may be found on page bnl_04_2004_sx72su.htm

Summary

• This is an Single Event Effects test of the RT54SX72SU, 0.25 µm, UMC die for heavy ion exposure.  Only results from the upset portion of the test will be reported here.  This test was run with both minimal supply voltages for the SEU portion of the tests and maximum voltages for the unprogrammed antifuse portion of the test.
• The test was conducted at the Brookhaven National Laboratory on April 30, 2004 and was a joint effort between the NASA Office of Logic Design and Actel Corporation. 
• No clock upset was detected.
• No loss of control (e.g., JTAG upset, etc.) was detected.
• Based on the data, the few upsets detected were likely a result of single event transients and not in the TMR-based R-Cell.

Device: RT54SX72SU

Package: CQFP256

Serial Nos.

LAN7001, D/C 0410
LAN7002, D/C 0411
LAN7003, D/C 0411

L/C: DOY311

Test frequency: Varied, see chart below.

Ions used: Bromine and Iodine

Antifuse rupture: Detected.

SEL: Not detected.

Loss of control, i.e., JTAG upset: not detected.

(Note for SEU testing; that data will be supplied in a separate report).  Since the K-Latch uses redundant structures, the angle of rotation can be critical to making an accurate measurement. This includes not only the magnitude of the angle and the range of the ion, but also the direction of the rotation. The redundant K-Latch circuits are implemented with the redundancy in the "long" direction of the die, as showed in the figure below.

Testing was performed rotating the DUT in two directions.  The main angle, which is normally used at BNL, is rotation, and is around a vertical axis as shown below.  The second axis used was roll.  Roll is about an axis that is perpendicular to the part - that is, in the direction of the beam.

   ++++++++++++++++++++++++++++++++++++++
   +                                    +
   +               DIE                  +
   +                                    +
   +                                    +
   ++++++++++++++++++++++++++++++++++++++
   ^                 ^
   |                 |
   PIN 1             |
                     |
                     |
                     |
                     |

               axis of rotation

The beam is going directly into the screen.

  
RTSX72SU DUT and card.

Test Logic Design

The logic design, called TMRSXS, has four 100-bit (flip-flops) shift registers: SOFTA, SOFT, HARDA and HARD, which are clocked by a common clock.  Each bit in SOFTA is a D flip-flop constructed by a register cell.  A buffer separates each bit.  Because this buffer has only one fan-out, it permits the fastest type of connection, called a Direct-Connect.  DOC is the output of SOFTA.  SOFT is identical to SOFTA except that there are no buffers between the bits, so there are no Direct-Connects.  DOS is the output of SOFT.

 

Each bit in HARDA is triple module redundant (TMR) hardened at the user-level.  Note that the user-level TMR is different from the hard-wired TMR, which is transparently designed in each register cell.  Each user-level TMR bit consists of three flip-flops and two muxes and an inverter.  The first mux functions as a majority voter.  The second mux and the inverter function as a disagreement detector.  The outputs of all disagreement detectors in the register are logically input to an OR gate.  To detect SET, an extra buffer and inverter are added to the "clear" and "preset" pins of each user-level TMR bit.  Any ion strike on either the inverter or the buffer will potentially upset the three flip-flops simultaneously.  DOVH is the output of HARDA, and the output of the OR gate connected to all the disagreement detectors is 0_ERR.  HARD is similar to HARDA except that there is no additional SET detecting buffer or inverter in each user-level TMR bit.  DOH is the output of HARD, and the output of the OR gate connected to disagreement detectors is 1_ERR.

Test Design

10% de-rating of the nominal power supply, i.e. V_CCI/V_CCA = 4.5/2.25 V, is used for the worst-case scenario SEU measurement.  This is the minimum of the manufacturer's recommended operating range.

Physical orientation of the K-Latch based R-Cell.
The ion beam is going directly into the screen.

Test Data

Note:  Only low voltage SEU data is reported here for a worst-case test scenario.  Runs at high voltage and after the detection of rupture are documented in a companion report.

Bias Conditions: V_CCI = 4.5VDC.  V_CCA = 2.25VDC.

BNL Run	DUT	Ion	LET MeV-cm2/mg	Tilt Deg	Roll Deg	Fluence Ions/cm2	Upsets						Data Pattern	Clock Freq	Comments
							1_Err	DOC	DOVH	DOS	DOH	0_Err
851	LAN7001	Br-81	37.5	0	0	1.00E+07	0	0	0	0	0	0	Zero	10M
852	LAN7001	Br-81	37.5	0	0	1.00E+07	0	1	0	1	0	0	CB	10M
853	LAN7001	Br-81	37.5	0	0	1.00E+07	0	1	0	2	0	0	CB	10M
854	LAN7001	Br-81	43.3	30	0	1.00E+07	0	1	0	2	0	0	CB	10M
855	LAN7001	Br-81	53	45	0	1.00E+07	2	1	0	4	0	1	CB	10M
856	LAN7001	Br-81	53	45	-90	1.00E+07	0	1	0	2	0	0	CB	10M
857	LAN7001	Br-81	43.3	30	-90	1.00E+07	0	0	0	3	0	0	CB	10M
858	LAN7001	Br-81	43.3	30	-90	1.00E+07	0	0	0	0	0	0	CB	0.5M
859	LAN7001	Br-81	53	45	-90	1.00E+07	0	1	0	0	0	0	CB	0.5M
860	LAN7001	Br-81	53	45	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
861	LAN7001	Br-81	43.3	30	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
862	LAN7001	Br-81	37.5	0	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
863	LAN7002	Br-81	53	45	0	1.00E+07	0	2	0	4	0	1	CB	10M
864	LAN7002	Br-81	53	45	0	1.00E+07	0	0	0	2	0	0	CB	0.5M
865	LAN7002	Br-81	37.5	0	0	1.00E+07	0	1	0	0	0	0	CB	10M
866	LAN7002	Br-81	37.5	0	0	1.00E+07	0	0	0	1	0	0	CB	0.5M
867	LAN7002	Br-81	53	45	-90	1.00E+07	0	3	0	2	0	0	CB	10M
868	LAN7002	Br-81	53	45	-90	1.00E+07	0	0	0	0	0	0	CB	0.5M
869	LAN7003	Br-81	53	45	-90	1.00E+07	0	3	0	4	0	1	CB	10M
870	LAN7003	Br-81	53	45	-90	1.00E+07	0	0	0	0	0	0	CB	0.5M
871	LAN7003	Br-81	53	45	0	1.00E+07	0	0	0	2	0	3	CB	10M
872	LAN7003	Br-81	53	45	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
873	LAN7003	Br-81	37.5	0	0	1.00E+07	0	0	0	1	0	0	CB	10M
874	LAN7003	Br-81	37.5	0	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
875	LAN7003	I-127	59.7	0	0	1.00E+07	0	2	0	2	0	2	CB	10M
876	LAN7003	I-127	59.7	0	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
877	LAN7003	I-127	104	55	0	1.00E+07	0	1	0	0	0	2	CB	10M
878	LAN7003	I-127	104	55	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
881	LAN7002	I-127	59.7	0	0	1.00E+07	0	1	0	5	0	2	CB	10M
882	LAN7002	I-127	59.7	0	0	1.00E+07	0	0	0	0	0	0	CB	0.5M
887	LAN7001	I-127	59.7	0	0	1.00E+07	2	1	0	2	0	1	CB	10M

Notes and Analysis

1. The figure above shows the importance of the board orientation; it also shows the relative orientation of the board and the hard-wired TMR flip-flop or R-Cell, which logically has three sub-flip-flops, ff1, ff2 and ff3. Physically, each  master and slave latch is composed of three redundant and interlocked K-Latches.  Only when two or more of the sub-flip-flops suffer upsets simultaneously due to an ion strike, can the TMR flip-flop can have an upset. Thus the device  under test can not be rotated in an arbitrary single degree of freedom to increase the effective LET for SEU measurement.  Note also that by sweeping both roll and tilt, an ion can traverse several redundant elements.  Of course, this also reflects the natural space radiation environment.  The magnitude of roll and tilt is limited by shadowing of the socket.  Next generation boards will surface mount the DUTs.
2. The data in the table shows that the SEU-errors are relatively independent of the roll angles. This insensitivity to the board orientation can be explained by the physically wide separation of the redundant latches.  Three dimensional mixed mode simulation demonstrated that even at 0°-roll and 60°-tilt orientation, a single heavy ion with LET of 100 MeV•cm²/mg cannot upset the TMR flip-flop.
3. The DOC string (BUFD between R-Cells) had a total of 20 errors reported while DOS (R-Cell to R-Cell) had a total of 35.
4. DOVH and DOH show no SEU errors even for 10 MHz clock while DOS and DOC show noise level SEU errors for 0.5 MHz clock and observable SEU errors for 10 MHz. This indicates the SET detecting buffers and inverters in DOVH are not susceptible to ion strikes even with the high LET used in this test, and also that the SEU-errors in DOS and DOC are due to the SET inside the hard-wired TMR flip-flop.
5. There are very few SEU errors in 1_ERR and 0_ERR, even for 10 MHz clock.
6. The figure below shows the cross-section per flip-flop with respect to LET. In this Figure, the data are derived from the DOS and DOC data in table that use the checkerboard pattern and the worst-case bias scenario, i.e. V_CCI/V_CCA = 4.5/2.25 V. As shown by the legend, the points are experimental data grouped by DUT clock frequency; each data point represents the average of the three DUTs. Clearly, the cross-section, or SEU-error, is strongly dependent on the clock frequency. SEU-errors for 10 MHz clock is about an order of magnitude higher than SEU-errors for 0.5 MHz. In fact, 0.5MHz data are practically in the noise level since a single error in each run can be just a noise due to accelerator operation. SpaceRad 4.5 simulator performs the SEU prediction by applying Weibull parameters to GEO solar-minimum environment with 100-mil Al shielding; the SEU rate is 3.93x10^-12 upsets per bit-day for 10 MHz, and 2.2x10^-14 upsets per bit-day for 0.5 MHz.

 

 

 

Reference

"An SEU-Hard flip-Flop for Antifuse FPGAs," Katz, R, J.J. Wang, J. Mccollum, B. Cronquist, R. Chan, D. Yu, I. Kleyner, and W. Parker, 2001 MAPLD International Conference, September 2001, Laurel, Maryland.

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