(Courtesy of APL)
- J. D. Mellert, SEE-02-068, "Operation of 54SX32 Actel Test Chip to Characterize Ground Bounce", Sept. 2002.
- H. Johnson and M. Graham, High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993. ISBN 0-13-395724-1.
- H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990. ISBN 0-201-06008-6.
Ground bounce, potentially large enough to cause an error in sensing logic level, was observed within an Actel 54SX32A. The magnitude of bounce was a function of output driver slew rate - faster outputs increased the effect. I/O power supply voltage also affected bounce with more observed in the 5V than the 3V parts. Temperature dependence of ground bounce was more complex. Bounce appeared independent of temperature for low slew outputs and increased when the part was cold for PCI type outputs. However, the data indicated that for the high slew outputs bounce decreased when cold.
While simultaneously switched output (SSO) induced ground bounce was clearly observed, application functionality in many cases should not be compromised. Most designs have only a small number of potentially sensitive signals. Pin placement and driver slew selection can dramatically reduce bounce for those signals. An engineering peer review of preliminary pin assignments may be helpful in identifying these issues and developing solutions. In case of a problem discovered after pin assignments are frozen, changes within the FPGA such as adding internal delays to stagger outputs can lessen bounce. External filter components can also be used to reduce the impact of bounce. SSO induced ground bounce does occur but many design techniques can be applied to overcome this problem.
Ground bounce induced by simultaneously switching outputs (SSO) is a well-known phenomenon. Its effects have been observed and explained since high-speed CMOS circuits became widely used. Many manufactures have application notes describing the issue and analysis and discussions are widely available (see references 2 and 3 for example).
This memo concentrates on measurements of ground bounce effects but similar signal transients can also occur around the positive supply. Ground rather than supply bounce is studied because the most common digital logic specification (TTL) has less noise immunity for the '0' value near ground than for the '1' value near the supply. In addition, the parts evaluated in this study also appear to have slower rise time resulting in less supply than ground bounce.
SSO induced ground bounce was evaluated on two Actel 54SX32A parts; one programmed with 3.3V I/O and the other programmed with 5V I/O. The evaluation circuits described in reference 1 were used to measure ground bounce magnitude. Test vectors were generated to switch 14 'aggressor' outputs simultaneously and an adjacent 15th 'witness' output was driven low. Simultaneously switched outputs sent large currents through the chip's finite impedance package wiring and internal power distribution network. A potential difference was thus developed between the chip's internal ground and the external reference ground. The witness signal acted as a probe of the on-chip ground level so that this potential difference could be observed.
3.0 Experiment Description
Three types of output signals were studied; Low slew, Fast slew, and High slew PCI. A test fixture originally fabricated to test flight Actel FPGAs with the SOR Schlumberger SX100 digital tester was used for this work. Test vectors toggled outputs simultaneously so that ground bounce could be observed with a 500 MHz bandwidth oscilloscope and probes. Measured witness behavior was only slightly sensitive to oscilloscope probe grounding, which confirmed that the fixture boards were well suited to evaluate performance.
Two Actel 54SX32A parts were used to evaluate SSO induced ground bounce; one programmed with 3.3V I/O while the other operated with 5V I/O. Test vectors simultaneously toggled 14 outputs while an adjacent 15th output was driven low. The high slew PCI ground bounce was also observed with a 'quiet' witness near the ground pin used by the aggressor signals; a 'remote' pin located on an adjacent side of the chip but with an intervening ground between it and the aggressors; and finally, a 'distant' pin on the opposite comer of the test chip. A diagram of the test FPGAs illustrating the aggressor and witness signals is shown in Figure 1.
Figure 1. Pin diagram of test FPGA. Aggressor and witness signals
are labeled and power and ground connections are highlighted.
All Device Under Test (DUT) inputs were driven by the VLSI Tester. Aggressor and witness nodes were loaded only by tester and fixture capacitance. Based on tester and FPGA specifications, the load for each signal pin was estimated at about 40pF. Considerable ringing of all signals was seen. Low amplitude (-0. 1V), high frequency ringing (2-3ns period), and much higher amplitude (~1V), lower frequency oscillations (15-25ns period) were observed.
The high frequency ringing was consistent with signal reflections caused by round trip delay through about an 8" trace between the Actel pin and tester receiver. The tester hardware connected the receiver to the DUT though a controlled impedance line. A microstrip transmission line built with typical printed circuit board material (έr = 4.3) has a time delay of 55ps/cm. Thus, a signal transition took about 2.2ns to travel through this line and reflect back to the source, similar to the observed behavior.
Lower frequency oscillations were probably caused when the signal transition excited a resonance between the load capacitance and the transmission line inductance. 50Ώ microstrip has about 1.1pF/cm and 2.8nH/cm. Therefore the 8" line had a total capacitance of 22pF and inductance of 57nH. The Actel FPGA pin and tester electronics each contribute an additional 10pf so the total capacitance should be about 42pF. The entire structure thus resonated at f = 1/(2*pi*sqrt(LC)) = 105 MHz or a 9.5ns period; about half the period of the observed ringing.
Table 1 summarizes the ground bounce that was observed on the witness signal. Each row of the table contains the observations for a part operating with the indicated I/O ring power supply and temperature. Maximum positive and negative voltage excursions of the signal are reported for each type of output signal.
Table 1. Observed ground bounce on adjacent witness pin.
VCCI Temp low slew high slew PCI Pos(V) Neg (v) Pos(V) Neg (v) Pos(V) Neg (v) 3.3 room 0.90 -1.40 1.06 -1.52 1.28 -1.70 3.3 -45 °C 0.96 -1.62 1.20 -2.64 1.52 -1.70 5.0 room 1.58 -2.26 1.80 -2.32 1.88 -2.48 5.0 -45 °C 1.58 -2.26 1.54 -2.56 1.86 -2.52
4.1 Output Slew Rate
The amount of observed ground bounce increased as the output signals were operated at faster slew rates. Bounce was also increased at higher operating voltage. Both observations were consistent with increased voltage drop across the FPGA power distribution wiring impedance caused by a higher peak current. When slew rate increased, the charge stored on the load was switched through the power network more quickly and hence peak current was larger. When operating voltage increased, peak current also was larger since additional charge was moved during a similar duration switching event.
Temperature also affected ground bounce although less dramatically than choice of output slew rate or operating voltage. Silicon MOSFET transistor carrier mobility increases as temperature is lowered. In the absence of slew limiting circuits, peak load currents increase and more ground bounce should be observed as the part is cooled.
When operated with a 3.3V power supply, positive bounce (i.e. an increase of witness voltage above ground) caused by PCI type signals increased as temperature was reduced as predicted by this theory. 5V PCI outputs also caused more ground bounce than 3.3V outputs. However, bounce was not affected by temperature for 5V PCI outputs. Some additional circuitry may be present that controlled load current at the higher supply voltage. The effect of temperature on ground bounce is more complex for high slew outputs. When operated at 3.3V, bounce was increased at cold temperature as expected. However, positive bounce observed with 5V high slew outputs appeared to decrease while negative bounce increased. We currently have no hypothesis to explain this observation.
Positive ground bounce was insensitive to cold temperature for low slew outputs operated at either 3.3V or 5V. This result implies that the low slew drivers probably contain circuitry to deliberately limit falling edge speed. Therefore, boards using the low slew outputs of the SX32A successfully operated at room temperature probably are also not affected by ground bounce when cooled. Data for high slew and PCI outputs showed that proper operation at both room and cold temperature should be confirmed to demonstrate that the design is not affected by ground bounce.
4.3 Shielding effects
Observed ground bounce was dramatically reduced for witness signals shielded from simultaneously switching outputs by intervening pins. As shown in Table 2, collected data indicated that bounce was reduced for signals close to a ground pin even without any other intervening grounds. Since the high slew PCI output case generated the largest amount of bounce, some additional witness signals were studied to assess the sensitivity of ground bounce to intervening pin connections.
Table 2. Shielding of high slew PCI SSO induced ground bounce.
Witness Type Pin # Pos (V) Neg (V) Adjacent 192 1.28 -1.70 Quiet 187 0.51 -0.77 Remote 19 0.40 -0.66 Distant 122 0.23 -0.34
Bounce was reduced from 1.28V at a pin adjacent to the aggressors, to only 0.51 V at a 'quiet' pin located 6 below the switching outputs and 2 above the nearest ground connection. This observation indicated that around half of the ground bounce observed at the adjacent pin was due to voltage drop across the chip's internal power distribution network. The remaining drop occurred across the bond wire and package impedance. Both the remote and distant witness sites saw much lower perturbations that would not be expected to cause any additional logic errors.
A design's functionality may be affected by ground bounce caused by simultaneously switching Actel 54SX32A FPGA outputs. However, the impact of ground bounce is very design dependent and is likely to be negligible for many designs. Commonly, a design will simultaneously switch a group of outputs when driving parallel lines, for example, a processor memory address/data bus. The bus value is subsequently sensed after time is allocated for transients, including ground bounce, to settle. Hence, bounce on the bus signals themselves is not significant for this design. Bounce induced in control signals used by external circuits to sample the bus may have more impact since a value may be prematurely sampled. Again, specifics of the design must be understood to determine if that error could cause improper operation.
After analysis, if a design is thought to be sensitive to simultaneously switched output induced ground bounce, a variety of approaches can be taken to reduce the effect's impact. Proper board layout with maximum use of ground and power distribution planes and power supply bypass filtering should always be used with fast logic parts such as the 54SX32A FPGA. Outputs should be configured to use the low slew output option whenever possible to minimize the transient currents that cause ground bounce. Control lines should be shielded by intervening ground pins if possible or, as a minimum, placed as close as possible to a ground pin to reduce the impact of SSO. Future FPGA applications may benefit from an informal engineering peer review of pin assignments to minimize the impact of simultaneously switched outputs induced ground bounce.
If FPGA pin assignment and driver selection can not be changed, internal design changes are still be feasible to reduce sensitivity to ground bounce. Outputs can be switched in smaller groups to avoid the large peak currents that cause bounce. Even small delays between the output enable signals applied to groups can reduce ground bounce. Such delays can be generated either synchronously or even with delay buffers as long as the delay is comparable to the output transition time.
External components may also reduce ground bounce. A small resistor in series with each of the simultaneously switched outputs forms a low pass filter with the load capacitance. A 40Ώ resistor with 50pF load capacitance has a time constant of 2ns, comparable to the fall time of the output, and should reduce peak ground current and bounce by about a factor of two. Alternatively, an inadvertently transitioning control signal could be filtered with a series resistor. Additional load capacitance on the sensitive signal may also reduce the ground bounce.
Ground bounce was observed and understood soon after the introduction of the earliest high-speed CMOS integrated circuits. Application notes discussing the phenomenon have been written by many manufacturers and the topic is covered in numerous textbooks (References 2, 3). ASIC designers routinely consider potential ground bounce issues when selecting a chip's package, determining signal pin assignments, and designing on-chip I/O circuits. The measurements described here show that FPGA designers for space applications now must also include ground bounce considerations in their work.
Last Revised: February 03, 2010
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