A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

AX LVDS Input Speed Test

Summary of Test and Results

A set of test chips were designed to get an "engineering feel" for how fast of a signal we can get onto an RTAX-S field programmable array.  For such a high-speed application, the LVDS input was selected for evaluation.  For time and cost reasons, we used a commercial AX250 device (standard speed grade) for evaluation.

Test chip #1 consisted of an LVDS input and a hand-placed 8-stage ripple counter (divide by 256).  A multiplexor controlled by a command over a UAR/T allowed us to switch any of the ripple counter's outputs to the output pin.  The purpose of the ripple counter and multiplexor was to allow us to observe the circuit's behavior by looking at signals of a reasonable frequency.  Result: Steady operation at room temperature and nominal voltage conditions was achieved at an input pulse rate up to 600 MHz.

Test chip #2 consisted of the same LVDS input, an on-chip Phase Lock Loop configured to multiply the frequency by 10, and the same hand-placed 8-stage ripple counter, multiplexor and UAR/T.  The goal of this test chip was to help determine what were the speed limiting factors for Test Chip #1.  Result: Steady operation at room temperature and nominal voltage condition was achieved at an internal frequency of 730 MHz.  Therefore, the core of the AX chip was not the limiting factor for Test Chip #1.  The limiting factor was either the LVDS input or the test set (test board, cables, or clock generator).

Some Details

Test Device: Actel AX250 in a PQ208 package, standard speed grade.  Date Code 0520.  The wafer was D19W01 for test chip #1 and ??? for test chip #2.

Test Board: Actel AX prototyping board.

Signal Source: Stanford Research Systems CG635 Synthesized Clock Generator (differential output).

Measurement Equipment: HP 54542C oscilloscope and Stanford Research Systems SR620 Universal Time Interval Counter (count mode).

Prototyping Board Used for Tests

Schematics:

Chip 1 schematic section.  LVDS input goes to a T flip-flop.l

Chip 2 schematic section.  Note phase lock loop between
the LVDS input and the T flip-flop.

Placement of x10 PLL and first divide-by-2 flip-flop.

The placement of the R-Cell and C-Cell for the
high-speed divide-by-2 flip-flop was intended
to maximize performance by using a Direct Connect.

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