Office of Logic Design Application Notes
Actelís high performance RTAX-S/SL devices are designed to be tolerant of any power-up or powerdown sequence. While this offers flexibility for the power supply design, designers need to be aware of several other factors, such as power supply sizing, appropriate point-of-load (PoL) DC/DC converters, ramp rates, and clean monotonic ramp-up and ramp-down of the various supplies. In general there is no power-up or power-down requirement for RTAX-S/SL devices but a spike in ICCA current is observed only at power-down when VCCDA powers down before VCCA. Data analysis indicates that the amplitude and duration of this ICCA transient depends
A test chip was designed to get an "engineering feel" for how fast we can make sequencers in the AX architecture. Performance of a power-on reset circuit and a 10-stage ring counter was measured. The limits of the on-chip PLL were explored. A set of test chips were designed to get an "engineering feel" for how fast of a signal we can get onto an RTAX-S field programmable array. A 600 MHz rate was achieved, limited either by the LVDS input or the test set. Abstract:
A sampling of waveforms from the LOLA flight model. Outputs of 54ACS132 and RTAX2000S (high and low slew) included.
May 9, 2006
This notice is to inform you that in order to ease design constraints on power supply, Actel has analyzed and modified the guidelines for VCCA for the RTAX-S product family. The absolute maximum voltage has been relaxed and provision has been made for a transient from an SET on the power supply. The recommended operating conditions have not been changed.
Anomalous ICCA current increases have been observed in RTAX-S FPGAs. The cause for this current increase was due to the routing tie offs in the devices non-hardened FIFO controller that had been modified to improve programming time in an early version of the software. Designer v7.0 SP1, released in March 2006, and later versions of the software include a routing modification that eliminates the anomalous current increases. Designers who are unable to update with the Designer software on their current project can avoid the SEU induced current increases by instantiating all available SRAM blocks in the target RTAX-S device.
- This set of charts is extracted from Dan Elftmann’s presentation at the “RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application Briefing” held at the NASA Goddard Space Flight Center on May 10, 2006.
- The charts here will address solely the resolution of the increase in RTAX-S FPGA current as seen in heavy ion testing and reported at an earlier Briefing. There, the theory was that a change in tie-offs for unused logic caused contention and the increase in current. These charts provide experimental data.
This application note describes provisions for transients on the core logic voltage, VCCA, which are induced by single event transients (SETs).
February 28, 2006.
Each Actel device has a “silicon signature” area, where manufacturing information is programmed at the factory. Actel has recently begun adding information indicating the wafer location of each die to the silicon signature of RTAX-S and RTSX-SU space-flight FPGAs. The additional information is included for failure analysis purposes and has no effect on the functionality or operation of the FPGAs.
OLD News #18, "New FPGA Technologies: Currents, Voltages, and Temperatures," described in part the increase in standby currents for some of the new FPGA technologies. This note will present some sample RTAX-S ICCA and ICCI data. It is clear that for many missions the standby currents will be considerably less than the specification limit since the ambient temperatures will be considerably lower then 125 ļC.
The RTAX-S series of FPGAs, like many sophisticated digital devices, has multiple ground pins and multiple ground signals. For RTAX-S, these are the quiet ground, the I/O driving grounds, and a ground for the logic array circuits. The following sections detail which device "pins" are connected to each ground.
These notes are intended to supplement the manufacturer's material on the RTAX-S Action Probe, giving some insight and additional information.
The RTAX-S series of FPGA provides higher density devices than the previous RTSX-SU devices. This application note provides tables to permit estimates to be made of the logic densities of these new devices. It is clear that the device number scheme does not present an easy to use metric for estimating logic capacity.
AX series devices are often used for prototyping circuits that ultimately will fly using the RTAX-S series FPGAs. While there are a number of significant differences between AX and RTAX-S, this application note will address the PLL present in the AX and it's impact on prototyping RTAX-S systems.
In previous generation Actel FPGAs such as the RT54SX, the RT54SX-S, and the RTSX-SU, gold ball bonds were used on aluminum pads. A concern is the formation of intermetallic compounds. Early generation Actel devices utilized aluminum wires. AX FPGAs, used for commercial, industrial, and military applications, employ gold bond wires. The RTAX-S, designed for space applications, has been designed for aluminum bond wires. Sample images are posted.
Actel RTAX-S Application Notes
RTAX-S is Actel's latest FPGA family designed for space applications and is a derivative of the Actel Axcelerator FPGA family. The RTAX-S architecture is based on Actel's multi-featured, high-density AX architecture but with enhancements for a high level of single-even upset (SEU) immunity. To achieve this, some Axcelerator features were removed from the silicon and other features were further enhanced.
The purpose of this application note is to facilitate the prototyping process by highlighting the differences between RTAX-S and Axcelerator. This document supplements the Actel application note Prototyping RTAX-S Using Axcelerator Devices.
Prototype verification is an important step in system integration where accurate behavioral simulation and static timing analysis are crucial. Since the enhanced radiation characteristics of radiation-tolerant devices are not required in this prototyping phase of the design, commercial Axcelerator devices can be used. The prototyping flow presented in this application note is carefully designed to simplify the roadmap to production. The document describes the main architectural differences between the families and how to address the conversion issues that can occur as a result of these differences.
RTAX-S is a radiation-tolerant (RT) derivative of the popular Axcelerator FPGA family. This application note explains how RTAX-S has been designed for radiation-intensive environments. In addition, software and hardware mitigation techniques are provided for user-hardened and unhardened features. Also included are risk assessments of the different radiation-tolerant features with recommendations for mitigating these risks where applicable.
This application note describes the Low Voltage Differential Standard (LVDS) I/O capabilities of Actel's Axcelerator and RTAX-S device families. The application note begins by describing the LVDS signaling standard, then discusses detailed timing and board layout requirements, and finally provides a description of LVDS features unique to Axcelerator and RTAX-S.
Actel has chosen to use a combination of the Axcelerator standard SRAM circuits and an error detection and correction (EDAC) intellectual property (IP) core. The core is accessed via Actel's ACTgen Macro Builder software and implements a class of linear block codes called shortened Hamming codes (see the “Regular Hamming Codes and Shortened Hamming Codes” section). The SRAM/EDAC core combination greatly mitigates the effects of soft errors.
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