The RTAX-S series of FPGA provides higher density devices than the previous RTSX-SU devices. This application note provides tables to permit estimates to be made of the logic densities of these new devices. It is clear that the device number scheme does not present an easy to use metric for estimating logic capacity.
The two tables below show both in absolute and relative terms the logic capacities of the RTSX-SU and RTAX-S families. Data in Table II is normalized to the RTSX-32SU. Also note that there are some capacity improvements in the RTAX-S FPGAs that are not accounted for in the table. This extra capacity comes from RTAX-S architectural additions relative to the RTSX-SU:
Flip-flops in the I/O Cells (input, output, and enable registers)
Carry chain logic
Buffer modules in each super cluster and I/O cluster
Additionally note that each RAM block in RTAX-S consists of 4,608 bits. There is no block RAM present in RTSX-SU.
Table I. Architectural logic resources of RTSX-SU and RTAX-S
Table II. Architectural logic resources of RTSX-SU and RTAX-S normalized to the RTSX32SU
1The RTAX4000S is not a released product at the time of this writing (11/2005) but is included for completeness.
RTAX-S and AX Application Notes
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Last Revised: February 03, 2010
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