Dr. Rod Barto
NASA Office of Logic Design
The picture below shows the original board placement for a PCI FPGA. The issue with this arrangement is the electrical distance between the bypass capacitors and power pins. Pin 1 is at the right end of the top row, as noted. Called out are the vias for VCCA pin 78 and VCCA capacitor C78, and VCCA pin 184 and VCCA capacitor C110.
Original layout pattern for an FPGA implementing a PCI core.
Although the pin and capacitor vias look fairly close together, first note the small size of the traces from the pin lands to the vias. These traces will have higher inductance than is necessary. Next, note in the following figure, showing the VCCA plane (the gray is the copper), the electrical distances between the capacitor and VCCA vias. Vias that appear close together in the layout are actually separated by islands of vias.
Original VCCA (2.5V) Plane
The electrical distance (i.e., the distance that charge needs to travel from the capacitor to the pin) plus the size of the VCCA traces creates a high inductance path for the current supplying the FPGA. Because the voltage drop across the inductance is V=L*di/dt, and di/dt is fairly high, this will create noise in the FPGA power distribution system. The situation for VCCI is only slightly better than VCCA (the FPGA requires both VCCA and VCCI).
The next figure shows the latest revision of the FPGA pattern being developed for a flight project's rework effort.
New and Improved footprint.
Pin 1 in this figure is at the top of the left row of pin lands. This pattern allows for 1 capacitor per power pin for a total of 15 capacitors. The original placement allowed for 1 capacitor per voltage per side, or 8 capacitors total, less than 1 capacitor per power pin.. Inductance is reduced by maximizing trace size and connecting each capacitor end to the appropriate planes with 2 vias. This revision requires a few minor tweaks, but is basically ready to use.
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