Inputs to most CMOS inputs have rise and fall time limitations for reliable operation. Although most if not all programmable logic devices have at least some hysteresis on their inputs, the transition time requirements vary considerably. Below is a table with input transition time requirements for many military and aerospace programmable logic devices.
The following are the symbols typically used for these parameters:
tR - rise time
tF - fall time
tT - transition time
Most specifications do not specify exactly how the waveform is measured. Generally, according to most data books, the time period recorded is between the 10% and 90% of the waveforms. Note that often a data sheet will specify that the parameter is listed as information only and are not tested. In laboratory measurements, especially for devices that are migrated to a faster process, it was shown that not all qualified devices fall within specification limits. Appropriate care should be taken with conservative margins.
If the input transition time requirement is not satisfied, generally two different effects can be seen. The first, more often seen in older technologies, is the ability to propagate non-logic levels. In the modern, faster technologies, the input stage will appear to oscillate. Based on the input stage design, the oscillation may not be directly observable on the input pin - making a simple scope measurement inadequate for design verification.
Normally, input transition time does not impact the design. However, there are several situations where appropriate care must be taken. Some of these are described below.
Pull-up Resistors: These are often used for tri-state or bi-directional busses. However, recall that the rise time of a pulled-up signal is t = 2.2RC, when measured between the 10% and 90% points on a waveform. For some of the devices, that is clearly significant. For example, suppose a bus signal has a capacitance of 50 pF and a pull-up resistor of 10 kohm is used, to keep power dissipation reasonable. This RC product results in a rise time of 500 ns. As seen in the chart below, this will violate the specifications of all of the recently introduced devices, with one device having a 10 ns requirement. One solution to this problem is simply not to use pull-up resistors and to utilize a bus hold or "keeper" circuit. This is easily constructed by connecting a resistor between the input and output of a buffer and connecting the buffer's input to the bus signal and ensuring proper voltage margins are maintained with the worst-case DC current draw. Often, this connection can be made using a spare FPGA I/O and a single device pin. Another alternative, used by the PCI protocol, is to actively drive the signal high before tri-stating the buffer. There is some level of risk for this circuit with various faults such as unexpected resets causing a driver, holding a line low, to tri-state.
Bus Hold Circuit
Filters: Filters are often included on signals for a variety of reasons such as the elimination of noise, ESD protection, etc. The transition times of these signals must be examined. Often, a discrete hysteresis buffer should be employed to present a clean sharp edge to the FPGA input, particularly for clock signals.
Interfacing with older logic families: This can lead to problems. Examining typical data for the CD4000B CMOS NOR gate, for VDD = 5V, the typical output transition time is 100 ns. For the CD4050B buffer, still in use to level-shift high voltage inputs, the room temperature, VDD = 5V supply voltage condition yields a worst-case transition time of 160 ns! Use of a hysteresis buffer such as the 54AC14 would be recommended for certain applications.
Input Transition Time Requirements for Military and Aerospace FPGAs and PALs
Act 3 - 0.8 Ám (5V)
Act 3 - 0.8 Ám (3.3)
A54SX-A (32, 72)
 ACT 1 Field Programmable Gate Arrays, March 1991.
 ACT 1 and ACT 2 Military FPGAs, April, 1992.
 ACT 1 Series FPGAs, April 1996.
 Radiation-Hardened FPGAs, v3.0, January 2000.
 ACT 2 Series FPGAs, April 1996.
 Accelerator Series FPGAs ACT 3 Family, September, 1997.
 54SX Family FPGAs RadTolerant and HiRel, Preliminary V1.5, March 2000.
 HiRel SX-A Family FPGAs, Advanced v.1, April 2000.
 RT54SX-S RadTolerant FPGAs for Space Applications, Advanced 0.2, November, 2000.
 QPRO XQR4000XL Radiation Hardened FPGAs, DS071 (v1.1) June 25, 2000.
 QPRO Virtex 2.5V Radiation Hardened FPGAs, DS028 (v1.0) April 25, 2000 Advance Product Specification.
 Not in data sheet.
 Configurable Logic Data Book, Atmel, August 1995.
 AT6000LV, Atmel, October 1999.
Some Sample Data
RT54SX16 output (bottom trace) with a slow rising input (top trace) which clocks a divide by two counter resulting in a "glitch." The clock input was provided by an HP8110A pulse generator.
NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
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