NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

TRST Pin for SX, SX-A, and SX-S Devices

Some models do not have a TRST* pin.  In this case, you can not be guaranteed that the TAP controller can not be upset and the device may lose control.

Note that the IEEE requires that, left unconnected, the TRST* pin pulls high, exactly the WRONG WAY.  Make sure that you have a good, solid pull-down to ground.  A piece of wire or a routing trace is appropriate.

Important: Note that some data sheets for the RT54SX16 and RT54SX32 state that the TRST* pin has a pin up on it; it does not and the data sheet is wrong.

There is no known, simple way to verify that the TRST* pin is active, as this pin can be used as an I/O.  Verification processes are under investigation.

From: http://www.actel.com/apps/guru/feb00/jy1316.html

How do I set the TRST pin during JTAG and Debug Mode for the RTSX, RTSX-S, and SXA devices?

RTSX rev1, RTSXS (also known as RTSX rev2), and SXA devices have a JTAG reset pin called TRST, which allows the user to asynchronously reset and hold the JTAG TAP controller in the Test-Logic-Reset mode (for more information, see JTAG Issues and the Use of RT54SX Devices) . TRST is an active low input. During JTAG testing and during Silicon Explorer debug mode, the JTAG state machine's reset must not be active, otherwise no testing can occur. Below is the recommendation for TRST pin in JTAG and Silicon Explorer.

  1. RTSX Rev0 - No TRST pin.

  2. RTSX Rev1 - Contains a dedicate hardwired TRST pin. There is NO internal pull-up resistor on TRST pin for this revision. User must tie TRST pin high when doing JTAG and Silicon Explorer. NOTE: RTSX32 devices are only in Rev1.

  3. RTSXS (also known as RTSX Rev2) - TRST pin is equipped with a pull-up resistor once it is configured as TRST. User can leave the TRST pin floating when doing JTAG and Silicon Explorer.

  4. SXA - TRST pin is equipped with a pull-up resistor once it is configured as TRST. User can leave the TRST pin floating when doing JTAG and Silicon Explorer.

Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz
NACA Seal