The old TIMER program used to include clock skew in the setup and hold time calculations. It appears that the new software no longer does this (trying to get that confirmed). Here's the output of the old software:
With the new TIMER you must pull out the clock skews and then put those into the hold time calculations. Here's a sample filter for a simple design along with an expanded clock path.
Now, to run some tests for the RT54SX72S, which has rather high skew on the routed array clocks, I designed a very simple circuit: two D flip-flops talking to each other. After that, I modified the circuit by placing a buffer element (BUFD) between the two flip-flops. The rows marked default used the automatic placement algorithm in Design, with no constraints. The "tweaked" versions utilize ChipEdit to move the hard macros and defeat the performance parts of the routing architecture, since we need to increase the minimum propagation delays to make hold time in the presence of skew.
For these tests, I used the RT54SX72S, speed grade 1, CQ208, best case, shortest speed. Libero version 2.2, service pack 1 was used for the analysis. Note that at this time Actel will not guarantee the minimum times coming out of the timing analyzer software.
Opposite edge clocking is a good skew-tolerant design technique. Here are two examples, one in schematic form and the other VHDL.
Process ( Clock, Reset )
if Reset = ActiveReset then
DTCountIntNE <= "00000000";
elsif Falling_Edge ( Clock ) then
if ReadPulse = '1' then
DTCountIntNE <= DTCountInt + 1;
End Process DTCountIntNEProc;
Process ( Clock )
if Rising_Edge ( Clock ) then
DTCountInt <= DTCountIntNE;
End Process DTCountIntProc;
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