NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

SX-A and SX-S Device Family Minimum Input Slew Rate.  Derived from laboratory data
under nominal conditions and not guaranteed.  All slew rates are in mV/ns.

From: schmitt_trigger.pdf

SX-S

Rise Time (SX-S)
I/O Buffer	PCI		TTL		CMOS
	3.3V	5.0V	3.3V	5.0V	5.0V
Inbuf	176	222	133	176	160
Clkbuf	10.5	16	8	10.5	N/A
Hclkbuf	14.7	27	14.7	27	N/A
Qclkbuf	10.5	16	8	10.5	N/A

Fall Time (SX-S)
I/O Buffer	PCI		TTL		CMOS
	3.3V	5.0V	3.3V	5.0V	5.0V
Inbuf	63	93	75	133	62
Clkbuf	10.5	16	8	10.5	N/A
Hclkbuf	14.7	27	14.7	27	N/A
Qclkbuf	10.5	16	8	10.5	N/A

SX-A

Rise Time (SX-A)
I/O Buffer	PCI		TTL
	3.3V	5.0V	2.5V	3.3V	5.0V
Inbuf	176	222	133	176	160
Clkbuf	10.5	16	8	10.5	16
Hclkbuf	14.7	27	8	14.7	27

Fall Time (SX-A)
I/O Buffer	PCI		TTL
	3.3V	5.0V	2.5V	3.3V	5.0V
Inbuf	63	93	38	75	133
Clkbuf	10.5	16	8	10.5	16
Hclkbuf	14.7	27	8	14.7	27

Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz