Recently one project had a condition where input levels were not at a good logic level and anomalous ICCI currents were observed. Based on previous results, it was expected that delta ICCI values should be on the order of 1 mA/input. The currents observed in the system under test represented current levels per pin of more than an order of magnitude higher. Since the previous values were based on older families and a simulation of the RT54SX-S FPGAs, a sample pin was chosen on an available RTSX32SU device. The results are presented below.
As can be seen, the current level peaks at approximately 2 mA for the one pin, with the pin's input oscillating.
Note that a non-logic level on an unterminated global clock pin in this technology can consume many tens of milliamps of current, since the entire clock distribution system will have many rapid transitions during the periods of oscillation. That is why the unused clock pins in the RT54SX-S and the RTSX-SU series must all be properly terminated.
The previous simulation work, mentioned above, was performed as part of a reliability study of unterminated inputs.
Update, February 20, 2005
A rescan of the Input vs. ICCI characteristics was performed, decreasing the step size by a factor of 10, to 10 mV, in the critical area around the switching threshold.
"RT54SX-S tR/tF Experiment," June 14, 2002.
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