The RT54SX72A and RT54SX72S has, in addition to the three global clocks, 4 quadrant clocks. These clocks may accessed via specific I/O pins or from signals internal to the logic array. Although logically equivalent, the timing performance for distributing one signal to multiple quadrants differs significantly depending on the method used. The design software may allocate a signal to multiple quadrant drivers automatically, even if sufficient resources are available to locate all flip-flops in one quadrant. A discussion of this architectural feature and sample performance numbers are given below.
QCLKBUF is the macro name when accessing a quadrant driver from an external pin. Similarly, QCLKINT is the macro name when accessing a quadrant driver from an internal logic signal. The software treats these two cases differently as there are significant electrical differences.
When a QCLKBUF is used, the back end software (Designer) does not constrain placement of the registers (when used in synchronous applications) to a particular quadrant. This is based on the electrical design of the device, where each of the four QCLKBUFs I/O cells has dedicated wiring (no programmable paths, metal) to each of the drivers that distribute the signal to the array. This keeps the skew from the I/O pin to the actual driver minimal. This can be seen in Figure 1, below, where each driver is preceeded by a 5:1 multiplexor, with 4 of those inputs being dedicated paths from the I/O pins.
Figure 1. QCLKBUF I/O cells and
QCLK distribution and driving
This results in moderately low skew. For a sample design, total skew was calculated across quadrants as a figure of merit. Note that for the purposes of timing calculations, only skew between sequentially adjacent flip-flops is used. For this sample design, with 59% R-Cell utilization, the worst-case skew was ~ 1 ns. Best-case skew was ~ 0.5 ns. For these calculations, "longest" was used and software version R1-2002 SP2.
When an internal signal is used to drive the quadrant clocks, the QCLKINT macro is used in the design, which instructs the Designer software to use the fifth input of the 5:1 multiplexor shown in Figure 1, above. Note that the routing uses local routing resources. In this case, the Designer software will not allow placement of flip-flops in multiple quadrants and will report an error if this is attempted.
If multiple quadrants are to be driven, then multiple QCLKINT macros must be used. From a timing perspective, this is the electrical equivalent of using high-skew, local routing resources to distribute a clock, since local routing resources are used to send the internal logic signal to the multiple quadrant drivers. The layout would look similar to Figure 2, below.
Figure 2. Distributing an internal signal to multiple quadrants
using quadrant drivers.
In this case, an INBUF is used to bring an external signal into the logic array, where
it is distributed to 3 QCLKINT macros for distribution to multiple quadrants.
Using an internal logic signal, local routing resources, and multiple QCLKINT macros, the logic design used in the example above was reanalyzed.
Worst-case (approximate, all times in ns, with software version R1-2002 SP2):
Quadrant Skew Min Max 1 1.1 2.22 3.29 2 1.0 2.55 3.54 3 1.0 8.18 9.18
Best-case (approximate, all times in ns):
Quadrant Skew Min Max 1 0.6 1.04 1.61 2 0.5 1.22 1.74 3 0.5 3.48 4.01
These sample timing numbers are a result of the device's architectural features. Within a quadrant, the skew is low, similar to the skew over the die, as a result of the low-skew quadrant driver. However, between quadrants, the skew is high, as would be expected when distributing a signal using high-skew, local routing resources. As a result, when using multiple QCLKINT macros to distribute an internally generated clock signal, very careful analysis must be used to ensure proper timing or skew tolerant design techniques should be used. Another option is to send the signal off-chip and then bring it back in using the QCLKBUF I/O macro.
Software Interface - Important Note
Currently, there is no notification given to the user when the design software uses multiple quadrant buffers for distribution of a signal brought into the chip through the QCLKBUF I/O macro. A request to Actel has been made to add notes to the log window and the design summary when this is done. When the QCLKINT macro is used, the software will not allow placement of R-Cells in multiple quadrants. A request was also made to be able to control the software on use of multiple quadrants for the QCLKBUF I/O module.
Specifying a Quadrant
In order to define the quadrant you want to use, you must unplace all of the modules in the current quadrant (including the QCLK driver), then place AND FIX one of them to the new quadrant and re-run layout.
Thanks to George Winkert of the NASA Goddard Space Flight Center for raising this issue and Jonathan Alexander for insight into the device architecture, notes, and sample calculations.
Please see the recently updated Actel note on this topic: qclk_e_reva.pdf
Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Digital Engineering Institute
Web Grunt: Richard Katz