Power Supply Sequencing (Note: Older datasheets are wrong!)
Unused_I/Os (Note: Actel application note is not accurate)
Prototype Page - Not Checked and Released
Last update: November 28, 2000.
There has been in a change in specification for Power Supply Sequencing of SX-series FPGAs. Previously, there were no specified restrictions on power sequencing for non-PCI SX-series devices; now there are restrictions. Failure to observe the correct power sequences can result in damage or potential stress to the device. SX-A series FPGAs, which include the SX-S device, have no power sequencing restrictions. A basic review of the power pins and their operation is given for SX and SX-A (SX-S) devices.
Two related series of devices have been developed, SX and SX-A. While they appear logically similarly architecturally, they do have significant electrical differences. There are also differences within a family. These differences include foundry, feature size, power supply voltages, input tolerance, output voltage swings, power sequencing, radiation-harness, and other factors. This application note will primarily address those factors involved with the power pins and I/O.
There are two general classes of devices: SX, and SX-A and of this revision, four feature sizes and two foundries. For this discussion, we shall exclude PCI compliant devices in many places as they are not involved in military or aerospace products. If there is a need for additional information, please e-mail me at maplug@pop700.gsfc.nasa.gov and I will research and include the needed information.
0.6 µm
These devices are the radiation-tolerant RT54SX16 and the RT54SX32 and are fabricated at the Matsushita Electric Company (MEC).
0.35 µm
These devices are the commercial grade A54SX08, A54SX16, and A54SX32. They are fabricated at Chartered Semiconductor (CSM).
0.25 µm
These devices are fabricated at the Matsushita Electric Company (MEC), for both the commercial (A54SXxx-A) and radiation-tolerant versions (RT54SXxx-A). Additionally, initial prototypes of the SEU-hardened version, the RT54SX32-S (really should be called RT54SX32-AS!!!) are produced on this line. Note that commercial grade A54SXxx-A devices can be fabricated in the 0.22 µm process described below.
0.22 µm
These commercial A54SXxx-A devices, marked the same as the 0.25 µm devices above, are fabricated at United Microelectronics Corp (UMC).
Note: Things are always changing so be sure to keep your information up to date.
All SX and SX-A (including SX-S) devices have three power supply pins in addition to ground. They are:
VCCI - Supply voltage for I/O's.
SX: VCCI = 3.3V
SX-A and SX-S: VCCI = 5.0, 3.3, or 2.5V1.
1VCCI = 2.5V for commercial devices only.
VCCA - Supply voltage for Array.
SX: VCCA = 3.3V
SX-A and SX-S: VCCA = 2.5V
VCCR - Supply voltage for input tolerance.
SX: VCCR = 5.0V
SX-A and SX-S: VCCR = No Connect.
Power Supply Tolerance for SX, SX-A, and SX-S
Commercial Industrial Military Temperature Range (C) 0 to +70 -40 to +85 -55 to +125 5.0V (%) ±5 ±10 ±10 3.3V (%) ±10 ±10 ±10 2.5V (%) ±8 ±8 ±8
Power Supply Sequencing (Note: Older datasheets are wrong!)
SX Devices (0.6 µm and 0.35 µm)
When powering up, VCCR must come up first and then VCCI and VCCA.
When powering down, VCCI and VCCA must go down first and then .VCCR
SX-A Devices (0.25 µm and 0.22 µm)
There are no requirements or limitations on power sequencing.
For SX and SX-A series devices, unused I/Os [this does not include CLK, HCLK, and QCLK in all models] may be left unconnected on the board design.
The output buffer for each I/O module is disabled - different than Act 1and Act 2 devices where they were programmed as active and driving low.
The input stage is disabled. The buffer is physically implemented as a NAND function and a fuse disables it, such that there is no totem-pole current.
The Actel guru system has a drawing of the I/O module and it's configuration when not used. This is incorrect and is shown below:
This drawing implies that the input buffer is floating and can not be terminated. Obviously, this configuration would lead to totem-pole current if the input would move from either of the rails [which can happen for a number of different reasons]. Furthermore, it would suggest that the design engineer needs to configure each unused I/O to prevent this condition. This should not be necessary.
Termination of CLK, HCLK, and QCLK Inputs (updated 6/28/01)
The HCLK input on all models, if not used, must be terminated by the user on the board. There is no output buffer available on chip to terminate the input.
For the CLKA/B inputs, for the RT54SX16, RT54SX32, and the RT54SX32S, the inputs, if not used, must be terminated by the user on the board; there is no output buffer available on chip to terminate the input. For the CLKA/B inputs on the RT54SX72S, the CLKA/B pins can be configured as user I/O. I have a letter into Actel to find out if the software will automatically terminate these particular inputs if unused - they state that the user should terminate these pins.
For the QCLKA/B/C/D inputs in the RT54SX72S, the inputs, if not used as quadrant clocks, can be configured as user I/O. Current software will not terminate these outputs for you and the user must do so on the circuit board. A pull-down resistor is recommended as "normal" Actel software terminates unused pins to ground through an OUTBUF driving low, and this will help keep designs compatible with any future software changes.
This information is current as of the latest data sheet available, version "Advanced v0.2."
I am following up on these topics.
Table Indicating Whether Unused Clock Needs Termination On Board
Part Number HCLK CLK A/B QCLK A/B/C/D RT54SX RT54SX16 Yes Yes N/A RT54SX32 Yes Yes N/A RT54SXS RT54SX32S Yes Yes N/A RT54SX72S Yes Yes* Yes* * A pull-down resistor is recommended or an OUTBUF can placed on the pad, driving it to a valid logic state.
Table Indicating Whether Unused Clock Can Be Configured As User I/O
Part Number HCLK CLK A/B QCLK A/B/C/D RT54SX RT54SX16 No No N/A RT54SX32 No No N/A RT54SXS RT54SX32S No No N/A RT54SX72S No Yes Yes
SX Devices (0.6 µm and 0.35 µm)
All non-PCI devices have 5V-tolerant inputs.
PCI devices are only available in commercial versions.
These devices are not hot swappable and are not capable of cold sparing.
SX-A Devices (0.25 µm and 0.22 µm)
All devices have 5V-tolerant inputs.
These devices are hot swappable and are capable of cold sparing.
SX Devices (0.6 µm and 0.35 µm)
- tR and tF must be < 50 ns
SX-A and SX-S Devices (0.25 µm and 0.22 µm)
- tR and tF must be < 10 ns
Input Thresholds (SX-A and SX-S)
HELP!!!!!!!!!!!!! Going through my notes, I have the following questions, am a bit confused, trying to sort out 4 data sheets and notes!
Individually selectable input buffer trip points except for the HCLK, RCLK, and DCLK clock buffers, which are globally set by programming the SSIG fuse).
For logic levels, we have in the notes:
3.3V PCI
LVTTL
5V PCI/TTL
5V CMOS (SX-S Only) Clock inputs not supported.
Can we still get all of those and drive outputs to 5V?
SX Devices (0.6 µm and 0.35 µm)
VIH = 2.0V
VIL = 0.8V
SX-A Devices (0.25 µm and 0.22 µm) and SX-S
VCCI = 5.0V
VIH = 2.0V
VIL = 0.8V
VCCI = 3.3V
VIH = 0.5 VCCI
VIL = 0.3 VCCI
VCCA VCCR VCCI Output Swing 0.6 µm 3.3 5.0 3.3 3.3 0.35 µm 3.3 5.0 3.3 3.3 0.25/0.22 µm 2.5 NC 5.0 5.0 2.5 NC 3.3 3.3 2.5 NC 2.51 2.5
1 - for commercial device only.
Is this correct and accurate? HELP!!!!!!!!!!!!!!!!
SX
Not power-up safe. The user must protect critical system resources during the power up and down transients. The output of the device during the transition is not defined.
SX-A and SX-S
Power-up safe. Each output driver is put into tri-state during the power transition. Weak pull-up or pull-down resistors can be programmed for each I/O pin.
Laboratory experiments on RT54SX32S devices have shown some anomalous behavior.For the RT54SX32S devices that were tested, if VCCI is applied before VCCA, then there can be some DC current draw on the VCCI supply pins. The amount of current was part dependent and ranged from approximately 1 mA to over 10 mA. Applying VCCA would cause the current into the VCCI supply pins to return to expected values. The amount of current was also a function of VCCI, with higher voltages on VCCI resulting in higher currents. The laboratory tests included voltages in the range of 2.25 V < VCCI < 5.5 V.
A white paper on JTAG and SX is available at: JTAG_SX_WhitePaper.PDF
A. TRST* pin.
Some models do not have a TRST* pin. In this case, you can not be guaranteed that the TAP controller can not be upset and the device may lose control.
Note that the IEEE requires that, left unconnected, the TRST* pin pulls high, exactly the WRONG WAY. Make sure that you have a good, solid pull-down to ground. A piece of wire or a routing trace is appropriate.
Important: Note that some data sheets for the RT54SX16 and RT54SX32 state that the TRST* pin has a pin up on it; it does not and the data sheet is wrong.
There is no known, simple way to verify that the TRST* pin is active, as this pin can be used as an I/O. Verification processes are under investigation.
From: http://www.actel.com/apps/guru/feb00/jy1316.html
How do I set the TRST pin during JTAG and Debug Mode for the RTSX, RTSX-S, and SXA devices?
RTSX rev1, RTSXS (also known as RTSX rev2), and SXA devices have a JTAG reset pin called TRST, which allows the user to asynchronously reset and hold the JTAG TAP controller in the Test-Logic-Reset mode (for more information, see JTAG Issues and the Use of RT54SX Devices) . TRST is an active low input. During JTAG testing and during Silicon Explorer debug mode, the JTAG state machine's reset must not be active, otherwise no testing can occur. Below is the recommendation for TRST pin in JTAG and Silicon Explorer.
RTSX Rev0 - No TRST pin.
RTSX Rev1 - Contains a dedicate hardwired TRST pin. There is NO internal pull-up resistor on TRST pin for this revision. User must tie TRST pin high when doing JTAG and Silicon Explorer. NOTE: RTSX32 devices are only in Rev1.
RTSXS (also known as RTSX Rev2) - TRST pin is equipped with a pull-up resistor once it is configured as TRST. User can leave the TRST pin floating when doing JTAG and Silicon Explorer.
SXA - TRST pin is equipped with a pull-up resistor once it is configured as TRST. User can leave the TRST pin floating when doing JTAG and Silicon Explorer.
B. TCLK pin.
Be sure that the driver into the TCLK pin is isolate and not connected to the system clock. If the two clocks are the same signal, then if there is a "JTAG upset" then the system clock pin can turn into an active output, shutting down the system clock. The part then can not recover into the TEST-LOGIC-RESET state.
C. Design database configuration and verification.
It is critical that the JTAG configuration be specified correctly in your design database.
When you import your netlist and set up the device, make sure that the Reserve JTAG pins options is set. This is not the default. Your JTAG TAP controller may lose control and circuit board level inputs can be ignored if this is not configured correctly. Here's a screen shot from R3-1998 showing how the software defaults into a potentially dangerous condition:
You can verify that the part is specified correctly by doing a Reports => Status command and look at the layout variables:
***** Layout Variables ************
Mode: STANDARD Incremental: OFF
Restrict JTAG Pins: YES Restrict Probe Pins: YESIf the part is not configured correctly, then you can go back through the Options => Device Setup Wizard and get back to the Device Variations form above.
A common question is decoding the numbers on the back of the part to identify the foundry. Perhaps we should include that here. I have parts from each of the different types of parts but perhaps putting in the general numbering scheme would help.
Note that commercial and military devices are often not the same. While in many cases in the industry, a device procured for military and aerospace applications is often simply packaged differently and a screened version of its commercial counterpart, that is not always true for these devices. Please read the proper specifications carefully.
One difference is antifuse radiation hardness. The RT series antifuses are radiation-hardened while, so far, the commercial versions appear to be radiation-tolerant. Again, check specific data sheets. Lot specific radiation test data may be required for this and other parameters.
Some devices and all RT devices (after initial silicon) include the TRST* pin for the IEEE 1149.1 TAP controller, allowing the TAP controller to be held in reset and be immune to single event upset (SEU) and loss of functionality. For more information on JTAG and SX technology, please see: ../SX_Series/JTAG_SX_WhitePaper.PDF. Please ensure that the Designer option to reserve pins for JTAG is enabled.
Devices fabricated on 0.6 and 0.3 µm technology use LOCOS isolation. 0.25 and 0.22 µm devices use shallow trench isolation.
For radiation test data, please see FPGA and ASIC Main Page - SX Series Rad Data and FPGA and ASIC Main Page - SX-A Series Rad Data.
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