Abstract:

In this seminar particular engineering aspects of the the Lunar Orbiter Laser Altimeter (LOLA) Digital Unit design will be presented. Design techniques, approaches, and features will be discussed which are of general interest to the digital logic design of flight digital electronics.

The LOLA Digital Unit design is constructed in a simple but flexible and powerful architecture.  The technologies used as the foundation of the electronics include 3 modern FPGAs, a custom-designed embedded microprocessor, a stand-alone MIL-STD-1553B communications chip (e.g., no processor or external memories needed), and a variety of logic blocks and communications interfaces.  The discussion will include design for testability and fault-tolerance and redundancy techniques, for instrument electronics that are "on a budget."

"Engineering Aspects of the Lunar Orbiter Laser Altimeter (LOLA) Digital Unit Design"

Richard Katz, Igor Kleyner, and Rod Barto
NASA Office of Logic Design

October 17, 2007, 10 am to 12 noon
NASA Goddard Space Flight Center

Presentation: lola_presentation_design_oct_2007.ppt

Abstract:

During the Apollo missions to the Moon in the 1960's and 1970's, a small custom processor called the Apollo Guidance Computer provided all onboard computations for Primary Guidance, Navigation and Control, and was built using a primitive gate array: the only logic elements were three-input NOR gates.

The Lunar Orbiter Laser Altimeter (LOLA) will be launched to the Moon in 2008 as part of the Lunar Reconnaissance Orbiter spacecraft and contains an embedded computer to perform real-time calculations to help control this scientific instrument.

LOLA's central processing unit (CPU) is a small, custom-designed processor, designed to meet the mission requirements while minimizing resources. This 8-bit machine is essentially code compatible with Intel's 8085 but is implemented in modern technology, an advanced, radiation-hardened 0.15 µm gate array, with the logic elements being a 4:1 multiplexor and a flip-flop.

For the rest of the abstract, please see: Back to the Moon

"Back to the Moon:
The Verification of a Small Microprocessor's Logic Design"

Hugh Blair-Smith
MIT Instrumentation Labs
NASA Office of Logic Design

September 19, 2007, 10 am to 12 noon
NASA Goddard Space Flight Center
Building 11, Directorate Conference Room

Presentation: Back to the Moon

Abstract

The ever-increasing size and complexity of designs is simply a fact of life. The only way to make sure that today’s (and tomorrow’s) designs will function correctly is to build a verification environment that allows you to adopt advanced verification technologies to augment your engineers’ ability to exercise the myriad scenarios under which your design is expected to operate. The question is how to adopt these technologies, like assertions, functional coverage, automated results checking, constrained-random stimulus generation and formal verification, with a minimum of hassle and in a complementary way so they can all work together.

This full-day tutorial will introduce you to each of these technologies, and show you an effective methodology for building a modular, reusable testbench environment that will enable you to adopt them effectively. We will start by introducing each of these technologies in the context of a high-level discussion of verification methodology. We will then provide an in-depth introduction to the IEEE 1800 SystemVerilog language, which provides explicit support for each of these technologies.

We will then proceed to a discussion of testbench architecture, and show how you can use SystemVerilog to build a transaction-level verification environment that allows you to verify designs at multiple levels of abstraction. The use of transaction-level modeling (TLM) for verification allows the testbench to be constructed in a way more consistent with how you think about the problem, and allows all verification components to communicate through consistent interfaces, which provides reusability. These concepts will be demonstrated by a practical example showing the verification of an FPU design implemented both at the transaction-level and in RTL (in VHDL). We will show how to architect the testbench to allow the same stimulus generators and results checkers to be reused, as well as how to use the original TLM as a golden reference model against which the RTL design will be compared.

Design Verification Tutorial

2006 MAPLD International Conference

Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum

Washington, D.C.

September 25, 2006

Abstract

Software allows unprecedented levels of complexity and new failure modes that are starting to overwhelm the standard approaches to ensuring system safety. The causes of accidents are even changing. This tutorial will cover fundamental concepts and techniques in building and ensuring safety in software-intensive systems, with particular emphasis on those aspects of complex systems not handled well by traditional system safety approaches, such as software requirements errors and accidents caused by dysfunctional interactions among components rather than component failure. While traditional system safety as applied to software and software-intensive systems will be covered, innovative, new approaches to hazard analysis, root-cause analysis, and risk management will be included.

Emphasis will be on procedures and techniques that are practical enough to be applied to projects today. Real project experiences with these techniques in different application areas will be described and recent software-related accidents will be reviewed and analyzed. You need not be a software engineer or programmer to understand the tutorial content.

This class is an abbreviated version of a week-long class that has been taught by Dr. Leveson for the past 15 years to over a thousand hardware and software engineers from 150 companies and government agencies.

Seminar: Systems Safety and Embedded Computing Systems

2006 MAPLD International Conference

Ronald Reagan Building and International Trade Center
with a session at the Smithsonian National Air and Space Museum

Washington, D.C.

September 25, 2006

 (posted by permission of the author)

"RTAX-S Boot Camp"

NASA Goddard Space Flight Center
Greenbelt, Maryland

May 9, 2006

Agenda

"Eclipse Boot Camp"

NASA Goddard Space Flight Center
Greenbelt, Maryland

May 11, 2006

Summary

This seminar is designed to provide conceptual and concrete techniques for ensuring that aerospace designs have “integrity” -- that is that they are definable, verifiable, maintainable, and efficient; and most important, that they WORK! The seminar will include three sessions. The first session is in two parts, the first part focusing on specification and design issues, the second on verification and validation (including related techniques). The second session will discuss power and signal integrity issues. The third session will consist of a panel discussion on the topic of FPGA verification with audience participation opportunity:

"Design Integrity Seminar"

2005 MAPLD International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 6, 2005

"This Is What We Find In This Stuff"

FY2005 Software/Complex Electronic Hardware Standardization Conference

Norfolk, Virginia
July 26-28, 2005

Logic_Course.ppt

"Fundamentals of Digital Engineering: Digital Logic, A Micro-Course"

NASA Goddard Space Flight Center
Greenbelt, MD
October 14, 2004
10 am to 11:30 am

Part 2 to be given December 9, 2004
Bldg. 11, AETD Conference Room
10 am to 11:30 am

Test methods, results, and implications will be discussed with respect to programmed antifuse reliability for the Actel RT54SX-S, RT54SX-SU, and the A54SX-A field programmable gate arrays.  Test plans covering the next several months will be presented.

"Actel RTSX-S and RTSX-SU Briefing"

NASA Goddard Space Flight Center
Greenbelt, MD
September 22, 2004

• Introduction and a VHDL Synthesis Issue
• A Designer's Checklist
• Methodologies for Reliable Design Implementation
  • VHDL Appendix
• Reset Circuit Topologies
• VHDL Design Tips and Low Power Design Techniques
• Synthesis Issues: Demonstrated with a Simple Finite State Machine Using Gray Codes
• VHDL Design Review and Presentation
• When Should You and When Should You Not Use VHDL?
• Case Study of a VHDL Design

"VHDL Synthesis for High-Reliability Systems"

2004 MAPLD International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 7, 2004

This seminar will start with an introduction into failure mechanisms and root cause analysis. Building from that base, a series of case studies will be examined in detail, exploring both the mechanisms and root causes and then discussing lessons learned from each of the mishaps. For many of the segments as possible, people involved in either the system or the mishap investigation will be presenting.

"Aerospace Mishaps and Lessons Learned"

2004 MAPLD International Conference
Ronald Reagan Building and International Trade Center
Washington, D.C.
September 7, 2004

Rich Katz
NASA Office of Logic Design
Tuesday, April 13, 2004

NASA Marshall Space Flight Center
Huntsville, AL
June 25^th, 2002

FPGAs in Space Environment and Design Techniques

Abstract

NASA Goddard Space Flight Center
Greenbelt, MD
Presented June 25^th, 2001

Programmable Logic in the Radiation Environment

"Programmable Logic in the Radiation Environment"

2002 MAPLD International Conference
Laurel, MD
September 9, 2002

Reliable Design (MSFC)

Abstract

"Advanced Design: Designing for Reliability, A Micro-Course"

NASA Marshall Space Flight Center
Huntsville, AL
June 11^th, 2001

Reliable_Design_Seminar

"Advanced Design: Designing for Reliability"

2001 MAPLD International Conference
Laurel, MD
September 10, 2001

Ground Bounce (pdf)
Ground Bounce (ppt)

NASA Goddard Space Flight Center
Greenbelt, MD
Posted: March 14, 2002

SDRAM (pdf)
SDRAM (ppt)

NASA Goddard Space Flight Center
 Greenbelt, MD
 Posted: March 19, 2002

Abstract

"Fundamentals of Digital Engineering: Digital Logic, A Micro-Course"

NASA Goddard Space Flight Center
Greenbelt, MD
Presented May 21^st, 2001

Abstract

"Programmable Logic Devices and Architectures: A Nano-Course"

NASA Goddard Space Flight Center
Greenbelt, MD
Presented March 5^th, 2001

"Programmable Logic Devices and Architectures"

2001 MAPLD International Conference
Laurel, MD
September 10, 2001

Clocking, Timing, and State Machine Seminar

"Logic Design: Clocking, Timing Analysis, and State Machine Design"

2002 MAPLD International Conference
Laurel, MD
September 9, 2002

"Introduction to Digital Systems Review"

This seminar is under development and will be presented on May 7, 2003, at the NASA Goddard Space Flight Center

Clocking, Timing, and State Machine Seminar

"Logic Design: Clocking, Timing Analysis, and State Machine Design"

NASA Goddard Space Flight Center
Greenbelt, MD

Part 1: March 18, 2003
Part 2: April 21, 2003
Part 3: May 29, 2003
Part 4: June 27, 2003 @ 10:30 am

"Advanced Design: Digital Signal Processing, Programmable Device Architecture, and Military/Aerospace Applications"

2003 MAPLD International Conference
Ronald Reagan Building and International Trade Center Washington, D.C.

September 8, 2003

"Reconfigurable Computing: FPGA-Based, General Purpose, High Performance Systems"

2003 MAPLD International Conference
Ronald Reagan Building and International Trade Center Washington, D.C.

September 8, 2003

Seminar Presentation

From Anonymity to Ubiquity: A Study of Our Increasing Reliance on Fault Tolerant Computing

Elwin C. Ong
Massachusetts Institute of Technology
NASA Goddard, Office of Logic Design

December 9, 2003