How Do You Review Someone Else’s VHDL Design?
Two Parts to the Answer
Basic Design Rule
Ideal Design/Review Flow
What is Design Review?
Most Superficial Review
Attending Peer Reviews
Most Detailed Review
In Any Event:
Who is the Reviewer?
Problems In Design Review
Designer’s Responsibilities
Two Reasons for Reviewability
Reviewer Response to Poor Documentation
Special VHDL Problem
Problem: Management Interference
Problem: Over-Reliance on Reviewer
Problem: Lack of Contractual Awareness
Problem: Lack of Analysis Standards
When Does Review Start?
Most Common Design Path
General Rules of Design Review
The Best Case
The Worst Case
Quick Design Assessment: The Finger Test
Tools for Analysis: Simulation (My own opinions, based on experience)
Tools: computer programs
Most Important Tool:
What VHDL Adds to the Review Process
VHDL Hides Design Details
VHDL is not WYSIWYG
VHDL and Bad Design Practices
Combined Effects of VHDL
Worst Case Result
Solution to VHDL Problem
Elements of Analysis
1. Part Parameters and Deratings
2. Timing analysis
Other Timing Analysis Items
3. Gate Output Loading
4. Interface Margins
Other Input Considerations
5. State Machines
6. Asynchronous Interfaces
7. Resets
8. Part Safety Conditions
9. Cross-Strap Signals
10. Circuit Interconnections
11. Bypass Capacitance Analysis
12. Special Pins
Email: rod@klabs.org
Home Page: http://klabs.org
Home Last Revised: February 03, 2010 Digital Engineering Institute Web Grunt: Richard Katz
