NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

Seminars for Programmable Logic and Military/Aerospace Systems

Virtex II: SEU's and Mitigation through TMR

November 9, 2004
NASA Goddard Space Flight Center
Bldg. 11, AETD Conference Room
9 am to 3 pm

Abstract

This full day seminar will concentrate on the use of Xilinx Virtex II FPGAs in the natural space radiation environment.  Specific topics to be covered include:

• What are the different classes of SEU's for the Virtex II FPGAs and what is the implication for each class of  upset?
• How does the "TMR tool" mitigate and eliminate upsets?
• Which class of upsets does the TMR tool not fix?
• What user considerations and impacts are there for using the TMR tool.

If you wish to attend and do not currently have access to the NASA Goddard Space Flight Center, please e-mail me.

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Last Revised: October 20, 2004
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