NASA Office of Logic Design

NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.


Independent Accelerated NASA Test of
Actel SX-A, SX-S, and SX-SU
Field Programmable Gate Arrays (FPGAs)

This page is used for the official dissemination of test status, results, and reports.

The NASA Office of Logic Design independent accelerated reliability test of Actel FPGAs is in progress and will evaluate A54SX-A, RTSX-S, and RTSX-SU devices.  The RTSX-S (MEC) and the RTSX-SU (UMC) are both 0.25 m devices.  A54SX-A devices are produced at both MEC (0.25 m) and UMC (0.22 m); only UMC A54SX-A devices are planned for evaluation at this time.

This is an accelerated test and the devices are subjected to higher stress levels than seen in our applications.  Thus, devices under test (DUTs) are subjected to environmental conditions ranging from -55 C to 125 C with each step being 250 hours in duration.  The first 1,250-hour segment consists of 250 hours of -55 C and 1,000 hours of 125 C exposure.  Additionally, other parameters are stressors, such as increased fanout, number of simultaneous switching outputs, amount of undershoot, and the supply voltage.  As the test proceeds, the DUTs will be subjected to additional test hours, increased voltage stress, increased node switching frequencies, an increase in the number of simultaneous switching outputs, and an increase in the amount of simultaneous undershoot.

Please note that the "Industry Tiger Team," led by the Aerospace Corporation, utilizes a different test vehicle and protocols and has different objectives than this test conducted by NASA.  As a result, there are a number of differences between the tests.  A description of the test vehicles can be found in:

"RTSX-S and RTSX-SU Reliability Test Vehicles"
Daniel K. Elftmann1, Richard Katz2, and Igor Kleyner2
1Actel Corp.
2 NASA Office of Logic Design
Presented at the 2004 MAPLD International Conference, September 8-10, 2004, Washington, D.C.

 

Related information

  1. Pictures of Test Hardware

  2. "Actel RTSX-S, RTSX-SU, and SX-A Briefing," September 22, 2004, NASA Goddard Space Flight Center

  3. "Actel RTSX-S and RTSX-SU Briefing," July 13, 2004, NASA Goddard Space Flight Center.

  4. "OLD News #16: Testing of Actel SX-A and RTSX-S Programming Algorithms," May 17, 2004

  5. "OLD News #15: Actel SX-A and RTSX-S Programmed Antifuses," March 17, 2004

  6. "OLD News #14: Testing and Application of Modern Microelectronic Devices: Do's, Don'ts, and Failures," November 19, 2003

  7. Temperature Chamber Map

  8. "Actel SX-A, RTSX-S, and RTSX-SU FPGAs in Mission- and Safety-Critical Systems: A Summary and Snapshot of a Dynamic Situation," November 3, 2004.

  9. Briefing: Independent NASA Test of RTSX-SU FPGAs, held February 16, 2005.

  10. tPD Summary: NASA Test of Actel SX-A, SX-S and SX-SU FPGAs

  11. Undershoot Conditions for the Independent Accelerated NASA Test of Actel SX-A, SX-S, and SX-SU Field Programmable Gate Arrays (FPGAs)

  12. Testing Summary: NASA Test of Actel SX-A, SX-S and SX-SU FPGAs

  13. "ESD Sensitivity of Actel RTSX-SU Field Programmable Gate Arrays," March 10, 2005

  14. Briefing: Independent NASA Test of FPGAs (May 11, 2005)

  15. Proceedings of the "Briefing: RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application (May 10, 2006).

  16. NASA2 Design, used for KU3 and KU4.  (May 12, 2006).


Testing Status

KU1 KU2 KM1 KM2 KM3 KM4 KU3 KU4

KM3 and KM4 will be MEC devices with the modified new algorithm (V3.89).
KU3 and KU4 will be UMC devices, new silicon revision, with both the UMC Modified Algorithm and the SAL.
KU3 and KU4 will use the NASA2 Design for the DUT pattern.

Testing Summary


Batch KU1: 150 RTSX32SU-CQ208B (D122H1) FPGAs have been programmed (October 16-17, 2004).  (anomalies)


Batch KU2: 150 RTSX32SU-CQ208B (D122H1) FPGAs have been programmed (November 4-9, 2004).  (anomalies)


 

Batch KU3:

Parts Information

Stimulus: CLKA / CLKB = 8 MHz (HTOL); CLKA / CLKB = 16 MHz (LTOL)

 


Batch KM1: 150 RT54SX32S-CQ208B FPGAs (New programming algorithm) - (anomalies)

Batch KM2: 150 RT54SX32S-CQ208B FPGAs (New programming algorithm) - (anomalies)

Batch KM3: 150 RT54SX32S-CQ208B FPGAs (Modified new programming algorithm - 3.90 (built 0623)) - (anomalies)

Batch KM4: 150 RT54SX32S-CQ208B FPGAs (Modified new programming algorithm - 3.90 (built 0623))

 


Home - NASA Office of Logic Design
Last Revised: February 03, 2010
Web Grunt: Richard Katz
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