Problem Description and Details
Actel performed ESD tests on 6 Field Programmable Gate Arrays (FPGAs) with p/n RTSX32SU-CQ256 using the HBM (Human Body Model) per MIL-STD-883F (Method 3015.7). The 3 FPGAs that were tested at 75 volt zap voltages all passed. Three other FPGAs had ESD test failures that were documented at the following zap voltages: 100V, 150V, and 200V.
An Actel failure analysis determined that the same transistor in the I/O structure was repeatedly identified to be susceptible to ESD damage. See Figure 1 (courtesy of Actel) below.
Since both the MEC and UMC I/O structures have identical form, fit, and function, ESD performance is similar.
As noted in reference 2, “out of family” but in specification leakage current has been documented in FPGAs. See Figure 2 below. ESD can cause such “out of family” performance degradation. Thus, handling FPGAs as minimally as possible in an ESD-free environment is very important for ensuring reliable device performance.
All NASA projects that use the Actel FPGA with p/n’s RT54SX32S, RT54SX72S, RTSX32SU, and RTSX72SU are advised to handle these devices using ESD procedures that can protect devices against ESD exposure at the less than 100V level. In addition to correctly fitted wrist straps and usage of ESD garments, it is recommended to use a calibrated air ionizer as a supplementary form of ESD protection. All FPGAs must be handled to the minimum extent possible.
Figure 1: SEM (40,000x Magnification) of Damaged Transistor. Courtesy of Actel.
Figure 2: “Out of family” but in specification ICCA value (25 mA max limit for leakage current)
- “Briefing: Independent NASA Test of RTSX-SU FPGAs,” February 16, 2005.
- “RT54SX-S & RTSX-SU ESD Performance,” February 16, 2005.
- “White Paper on Definitions and Approach to Anomaly Handling,” Professor Nancy Leveson, Aeronautics and Astronautics Department, MIT and Rich Katz, NASA Office of Logic Design, December 21, 2004.
- OLD News #11. “Interface Components and ESD,” May 28, 2003.
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Last Revised: February 03, 2010
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