NASA Office of Logic Design

A scientific study of the problems of digital engineering for space flight systems,
with a view to their practical solution.

ESD Sensitivity of Actel RTAX-S Field Programmable Gate Arrays

 

Three ESD Test Methods for Product Evaluation

• Human Body Model (HBM)     Þ Test Method 3015.7
• Machine Model (MM)         Þ JEDEC Specification JESD22-A115
• Charge Device Model (CDM)  Þ JEDEC Specification JESD-C101C

Model	HBM	MM	CDM
Performance Level	2000 V	250 V	750 V
	Class 1: 0 V to < 1,999 V	Class A: ≤ 200 V	Class I : < 400 V
	Class 2: 2,000 V to < 3,999 V	Class B: 200 V to > 400 V	Class II : 200 to < 500 V
	Class 3: ≥4000 V	Class C: ≥ 400 V	Class III: 500 to < 1000 V
			Class IV : ≥ 1000 V

Reference

1. This data is extracted from Dan Elftmann’s presentation at the “RT54SX-S, RTSX-SU, RTAX-S, and Eclipse FPGAs for Spaceborne Application Briefing” held at the NASA Goddard Space Flight Center on May 10, 2006.

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Last Revised: May 15, 2006
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